In-system Debug - 3.1 English - PG236

For in-system debugging, relevant information can be verified using UART before checking the hardware signals.

1. Press i to check the system information.
2. Press z to check the event log.

   The following table shows two examples of system flow event logs.

   Table 1. System Flow Event Log

   At System Start-up

   While Changing Video Stream from UART Menu

   VPHY log ------ GT init start GT init done RX frequency event RX timer event RX DRU disable CPLL reconfig done GT RX reconfig start GT RX reconfig done CPLL lock RX reset done RX MMCM reconfig done HDMI RX log ------ Initializing HDMI RX core.... Initializing HDCP 1.4 core.... Initializing AXI Timer core.... Initializing HDCP 2.2 core.... RX HDCP 1.4 Enabled RX HDCP 2.2 Disabled Reset HDMI RX Subsystem.... RX cable is connected.... RX HDCP 1.4 Enabled RX HDCP 2.2 Disabled RX HDCP 1.4 Enabled RX HDCP 2.2 Disabled RX TMDS reference clock change RX Stream Init RX Stream Start RX Stream is Up

   VPHY log ------ CPLL lost lock RX frequency event RX frequency event RX timer event RX DRU disable CPLL reconfig done GT RX reconfig start GT RX reconfig done CPLL lock RX reset done RX MMCM reconfig done HDMI RX log ------ RX Stream is Down RX Stream is Down RX TMDS reference clock change RX Stream Init RX Stream Start RX Stream is Up

   Table 2. System Flow Event Log (For Versal Pass-through Designs)

   At System Start-up

   While Changing Video Stream from UART Menu

   HDMIPHY log ------ GT init start GT init done TX frequency event TX timer event TX GPO Rising Edge Detected TX MMCM reconfig done GT TX reconfig done TX MMCM lock LCPLL lock TX reset done RX frequency event RX timer event RX DRU disable RX GPO Rising Edge Detected GT RX reconfig done RPLL lock RX reset done RPLL lost lock RPLL lock RX reset done RX MMCM reconfig done RX MMCM lock TX frequency event TX frequency event TX timer event TX GPO Rising Edge Detected TX MMCM reconfig done GT TX reconfig done LCPLL lost lock TX MMCM lock LCPLL lock TX reset done HDMI RX log ------ Initializing HDMI RX core.... Initializing HDCP 1.4 core.... Initializing AXI Timer core.... Initializing HDCP 2.2 core.... RX HDCP 1.4 Enabled RX HDCP 2.2 Disabled Reset HDMI RX Subsystem.... RX cable is connected.... RX HDCP 1.4 Enabled RX HDCP 2.2 Disabled RX HDCP 1.4 Disabled RX HDCP 2.2 Enabled RX TMDS reference clock change RX Stream Init RX Stream Init RX mode changed to HDMI RX Stream Start RX Stream is Up

   HDMIPHY log ------ TX frequency event RX frequency event RX frequency event RX timer event RX DRU disable RX GPO Rising Edge Detected GT RX reconfig done RPLL lock RX reset done RX MMCM reconfig done RX MMCM lock RX frequency event RX frequency event RX timer event RX DRU disable RX GPO Rising Edge Detected GT RX reconfig done RPLL lock RX reset done RX MMCM reconfig done RX MMCM lock HDMI RX log ------ RX Stream is Down RX Stream is Down RX mode changed to DVI RX TMDS reference clock change RX Stream Init RX mode changed to HDMI RX Stream Start RX Stream is Up RX Stream is Down RX Stream is Down RX mode changed to DVI RX TMDS reference clock change RX Stream Init RX mode changed to HDMI RX Stream Start RX Stream is Up

3. Press e to check the EDID.

   In this release, the application software reads and parses the sink EDID to determine the sink capability. However, the current application does not block you from setting certain video formats although it is not supported by the sink. Instead, a warning message is prompted to indicate the sink limitation when you type e.

   In this release, for the EDID parsing feature, three VERBOSITY levels are defined. You can set it according to your requirements. It is accessible from the video_common library, in xvidc_cea861.h.

   #define XVIDC_EDID_VERBOSITY          0

   where XVIDC_EDID_VERBOSITY is defined in the following table.

   XVIDC_EDID_VERBOSITY	Description
   0 (Default)	Read and parse the EDID No display of capability
   1	Read and parse the EDID Display of basic capability of the sink
   2	Read and parse the EDID Display of full capability of the sink

   Important: In the Example design running on MicroBlaze™ , limited BRAM resources are allocated to store the software binary. If you enable the XVIDC_EDID_VERBOSITY to a higher level, which consumes more software resources, you might need to increase the BRAM allocation. Otherwise, you might experience system instability such as UART hangs.
4. Press h to check the HDCP status.
   Note: The HDCP debug menu is not enabled by default. You can enable it by setting it in xhdmi_example.h.

   /* Enabling this will enable HDCP Debug menu */
   #define HDCP_DEBUG_MENU_EN 1

   Note: You must check the software size so that it does not exceed the allocated BRAM.
5. The default EDID in the HDMI example application does not support HBR. If you intend to bring up HBR feature in your design or Xilinx example design, ensure the HDMI RX EDID is updated to support HBR audio. Otherwise, some commercial HDMI sources cannot send out HBR audio. Some sources might even disable the HBR option from the menu.

   The EDID clone feature can be used in the example design to enable HBR in HDMI RX example design (pass-through topology). Perform the following steps to clone an EDID from an HBR audio receiver:

   1. Connect the HDMI TX to the HBR audio receiver
   2. Key in the HDCP Password (optional)
   3. Clone the EDID (In UART, press e, then press 2)
   4. Connect the HBR Audio Source to the HDMI RX