Navigating Content by Design Process - 2022.2 English

Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal® ACAP design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:

Hardware, IP, and Platform Development​

Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:

• Debugging the Design
• In-System Logic Design Debugging Flows
• Debugging Logic Designs in Hardware
• Viewing ILA Probe Data in the Waveform Viewer
• Debugging Designs Post Implementation

Board System Design

Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. Topics in this document that apply to this design process include:

• Programming the Device
• Remote Debugging in Vivado
• Programming Configuration Memory Devices
• Advanced Programming Features
• Serial Vector Format (SVF) File Programming
• Serial I/O Hardware Debugging Flows
• Debugging the Serial I/O Design in Hardware
• Device Configuration Bitstream or PDI Settings
• Low Level SVF JTAG Commands
• JTAG Cables and Devices Supported by hw_server
• Configuration Memory Support