Debug Hub - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
Release Date
2022.2 English

On 7 series and UltraScaleā„¢ architectures, the Vivado Debug Hub core provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA and the Vivado Debug cores including the following types of cores:

  • Integrated Logic Analyzer (ILA)
  • Virtual Input/Output (VIO)
  • Integrated Bit Error Ratio Tester (IBERT)
  • JTAG-to-AXI
  • Memory IP
    Important: The Vivado Debug Hub core cannot be instantiated into the design. It is inserted by Vivado during the opt_design stage.