Debug Core Clocks - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2022.2 English

All of the debug cores available in the Vivado IP catalog require a clock, that ensures synchronization with the input probes being monitored or any output signals being driven by the debug cores. During core discovery and debug measurement phase, it is expected that the clock is free running and stable. It is also expected that the clock is synchronous to the signals being monitored or driven. Failure to do so could result in cycle inaccurate data.

The Debug Hub IP bridges between host machine (through BSCAN Primitive which supports a serial interface) and debug cores on the chip (through XSDB interface which supports a parallel interface). The BSCAN primitive clock shifts the data in and out of the chip to the Debug Hub IP serially. The Debug Hub IP collects the data and sends it to all the debug cores on parallel interface using the Debug Hub clock and vice versa. If any of the debug core clocks are not free running or not stable, you end up with corrupted data which results in a "Debug Cores not detected" message. To avoid any corruption of data, it is important to ensure that the JTAG clock and Debug Hub clocks are stable and free running during the debug core detection process.

  1. The Debug Hub Clock must be free running and stable. Xilinx recommends that the clock be driven from a clock driver that is properly constrained and whose timing is met.
  2. If the clocks are driven from MMCM/PLL, ensure that the MMCM/PLL LOCKED signal is high prior to any debug core measurements. If the clock is connected to the Debug Hub or any of the debug cores and the MMCM/PLL LOCKED signal transitions to a 0 in the middle of debug operations, the clock can have significant jitter that might result in unpredictable behavior of the debug logic.
  3. In order to detect the debug cores, take measurements using those cores and capture data. It is required to have all the associated clocks free running and stable.

The following table lists the various debugging phases and the clocks required during the specific phases.

Table 1. Debugging Phase Clock Requirements
Debugging Phase JTAG Clock Debug Hub Clock Debug Core Clock 2
Connect to Target Stable 1 NA NA
Programming Stable 1 NA NA
Debug Core Discovery Stable 1 Stable NA
Debug Core Measurement 3 Stable 1 Stable 1 Stable
  1. Stable Clock: A clock that does not pause/stop during the event.
  2. Assumes the Debug Core Clock is different from the Debug Hub Clock.
  3. A Debug Core Measurement phase includes any step that does a get or set of properties on the debug core.