Probing the Design for In-System Debugging - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2022.2 English

The probing phase of the in-system debugging flow is split into two steps:

  1. Identifying what signals or nets you want to probe
  2. Deciding how you want to add debug cores to your design

In many cases, the decision you make on what signals to probe or how to probe them can affect one another. It helps to start by deciding if you want to manually add the debug IP component instances to your design source code (called the HDL instantiation probing flow) or if you want the Vivado tool to automatically insert the debug cores into your post-synthesis netlist (called the netlist insertion probing flow). The following table describes some of the advantages and trade-offs of the different debugging approaches.

Table 1. Debugging Strategies
Debugging Goal Recommended Debug Programming Flow
Identify debug signals in the HDL source code while retaining flexibility to enable/disable debugging later in the flow.

Use mark_debug property to tag signals for debugging in HDL.

Use the Set up Debug wizard to guide you through the Netlist Insertion probing flow.

Identify debug nets in synthesized design netlist without having to modify the HDL source code.

Use the Mark Debug right-click menu option to select nets for debugging in the synthesized design netlist.

Use the Set up Debug wizard to guide you through the Netlist Insertion probing flow.

Automated debug probing flow using Tcl commands.

Use set_property Tcl command to set the mark_debug property on debug nets.

Use Netlist Insertion probing flow Tcl commands to create debug cores and connect to them to debug nets.

Explicitly attach signals in the HDL source to an ILA debug core instance.

Identify HDL signals for debugging.

Use the HDL Instantiation probing flow to generate and instantiate an Integrated Logic Analyzer (ILA) core and connect it to the debug signals in the design.