The JTAG-to-AXI Master debug core is a customizable core that can generate the AXI transactions and drive the AXI signals internal to an FPGA at run time. The core supports all memory mapped AXI and AXI-Lite interfaces and can support 32- or 64-bit wide data interfaces.
The JTAG-to-AXI Master (JTAG-AXI) cores that you add to your design appear in the Hardware window under the target device. If you do not see the JTAG-AXI cores appear, right-click the device and select Refresh Hardware. This re-scans the FPGA device and refreshes the Hardware window.
Click to select the JTAG-AXI core (called hw_axi_1 in the following figure) to see its properties in the AXI Core Properties window.
