In-System IBERT System Serial I/O Design Debugging Flows - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2022.2 English
Important: The In-System IBERT core is only available for the UltraScale and UltraScale+ device families and is not supported on Versal device families as In-System IBERT functionality has been integrated into Versal IBERT.

The In-System IBERT IP lets you perform 2-D eye scans of UltraScale and UltraScale+ transceivers using the Vivado Serial IO Analyzer tool. This IP uses data from the design to plot the eye scan of the transceivers in real time while they interact with the rest of the system. This IP can be integrated with user logic in the design or Xilinx transceiver based IPs (for example GT Wizard or Aurora).

The In System Serial I/O Debugging flow has three distinct phases:

  1. In-System IBERT Core Generation phase: Customizing and generating the In-System IBERT core that best meets your hardware high-speed serial I/O requirements.
  2. Integration phase: Instantiating the IP and integrating it into your design.
  3. Serial I/O Analysis phase: Interacting with the In-System IBERT IP contained in the design to debug and verify issues in your high-speed serial I/O links.

Details about the In-System IBERT Core Generation phase and the Integration phase are covered the remainder of this section. For details of the Serial I/O Analysis phase, see Debugging the Serial I/O Design in Hardware.