From AXI to BSCAN - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
Release Date
2022.2 English

This bridge type is intended for designs using Xilinx® Virtual Cable (XVC) to remotely debug an FPGA or SoC device through Ethernet or other interfaces without the need for JTAG cable. In this mode, the Debug Bridge expects to receive Xilinx® Virtual Cable commands via AXI4-Lite interface. Use this mode to debug designs on the FPGA device over the Xilinx® Virtual Cable.

For more information, see the Debug Bridge LogiCORE IP Product Guide (PG245).

Figure 1. AXI to BSCAN Debug Bridge