Vivado Debug Bridge IP and Xilinx Virtual Cable (XVC) Flow - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2022.2 English
Note: Vivado Debug Bridge IP is not supported on Versal® devices.

The Vivado Debug Bridge IP core is a controller that provides multiple options to communicate with the debug cores in the design. This design can be a flat design or a Dynamic Function eXchange design. In addition, the Debug Bridge IP core can also be configured to take advantage of debugging designs using a JTAG cable or remotely through Ethernet, PCIe® , or other interfaces without the need for a JTAG cable.

Different modes in Debug Bridge IP facilitate the support of various use cases.