PLLE2_BASE - 2022.1 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)
Document ID
UG953
Release Date
2022-04-20
Version
2022.1 English

Primitive: Base Phase Locked Loop (PLL)

Introduction

PLLE2 is a mixed signal block designed to support frequency synthesis, clock network deskew, and jitter reduction. The clock outputs can each have an individual divide (1 to 128), phase shift, and duty cycle based on the same VCO frequency. Output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration.

PLLE2 complements the MMCM element by supporting higher speed clocking while MMCM has more features to handle most general clocking needs. PLLE2_BASE is intended for most uses of this PLL component while PLLE2_ADV is intended for use when clock switch-over or dynamic reconfiguration is required.

Port Descriptions

Port DIrection Width Function
CLKFBIN Input 1 Feedback clock pin to the PLL.
CLKFBOUT Output 1 Dedicated PLL Feedback clock output.
CLKIN1 Input 1 General clock input.
CLKOUT0 Output 1 Configurable clock output CLKOUT0.
CLKOUT1 Output 1 Configurable clock output CLKOUT1.
CLKOUT2 Output 1 Configurable clock output CLKOUT2.
CLKOUT3 Output 1 Configurable clock output CLKOUT3.
CLKOUT4 Output 1 Configurable clock output CLKOUT4.
CLKOUT5 Output 1 Configurable clock output CLKOUT5.
LOCKED Output 1 An output from the PLL that indicates when the PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The PLL automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (e.g., input clock phase shift). The PLL automatically reacquires lock after LOCKED is deasserted.
PWRDWN Input 1 Powers down instantiated but unused PLLs.
RST Input 1 The RST signal is an asynchronous reset for the PLL. The PLL will synchronously re-enable itself when this signal is released and go through a new phase alignment and lock cycle. A reset is required when the input clock conditions change (e.g., frequency).

Design Entry Method

Instantiation Yes
Inference No
IP Catalog Yes
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
BANDWIDTH STRING "OPTIMIZED", "HIGH", "LOW" "OPTIMIZED" Specifies the PLLE2 programming algorithm affecting the jitter, phase margin and other characteristics of the PLLE2.
CLKFBOUT_MULT DECIMAL 2 to 64 5 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency.
CLKFBOUT_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL.
CLKIN1_PERIOD FLOAT (nS) 0.000 to 52.631 0.000 Specifies the input period in ns to the PLL CLKIN1 input. Resolution is down to the ps (3 decimal places). For example a value of 33.333 would indicate a 30 MHz input clock. This information is mandatory and must be supplied.
CLKOUT0_DIVIDE, CLKOUT1_DIVIDE, CLKOUT2_DIVIDE, CLKOUT3_DIVIDE, CLKOUT4_DIVIDE, CLKOUT5_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT0_DUTY _CYCLE, CLKOUT1_DUTY _CYCLE, CLKOUT2_DUTY _CYCLE, CLKOUT3_DUTY _CYCLE, CLKOUT4_DUTY _CYCLE, CLKOUT5_DUTY _CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of the associated CLKOUT clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT0_PHASE, CLKOUT1_PHASE, CLKOUT2_PHASE, CLKOUT3_PHASE, CLKOUT4_PHASE, CLKOUT5_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL.
DIVCLK_DIVIDE DECIMAL 1 to 56 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
REF_JITTER1 3 significant digit FLOAT 0.000 to 0.999 0.010 Allows specification of the expected jitter on CLKIN1 in order to better optimize PLL performance. A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown. If known, then the value provided should be specified in terms of the UI percentage (the maximum peak to peak value) of the expected jitter on the input clock.
STARTUP_WAIT STRING "FALSE", "TRUE" "FALSE" When "TRUE", wait for the PLLE2(s) that have this attribute attached to them will delay DONE from going high until a LOCK is achieved.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- PLLE2_BASE: Base Phase Locked Loop (PLL)
--             7 Series
-- Xilinx HDL Language Template, version 2022.1

PLLE2_BASE_inst : PLLE2_BASE
generic map (
   BANDWIDTH => "OPTIMIZED",  -- OPTIMIZED, HIGH, LOW
   CLKFBOUT_MULT => 5,        -- Multiply value for all CLKOUT, (2-64)
   CLKFBOUT_PHASE => 0.0,     -- Phase offset in degrees of CLKFB, (-360.000-360.000).
   CLKIN1_PERIOD => 0.0,      -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
   -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
   CLKOUT0_DIVIDE => 1,
   CLKOUT1_DIVIDE => 1,
   CLKOUT2_DIVIDE => 1,
   CLKOUT3_DIVIDE => 1,
   CLKOUT4_DIVIDE => 1,
   CLKOUT5_DIVIDE => 1,
   -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
   CLKOUT0_DUTY_CYCLE => 0.5,
   CLKOUT1_DUTY_CYCLE => 0.5,
   CLKOUT2_DUTY_CYCLE => 0.5,
   CLKOUT3_DUTY_CYCLE => 0.5,
   CLKOUT4_DUTY_CYCLE => 0.5,
   CLKOUT5_DUTY_CYCLE => 0.5,
   -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
   CLKOUT0_PHASE => 0.0,
   CLKOUT1_PHASE => 0.0,
   CLKOUT2_PHASE => 0.0,
   CLKOUT3_PHASE => 0.0,
   CLKOUT4_PHASE => 0.0,
   CLKOUT5_PHASE => 0.0,
   DIVCLK_DIVIDE => 1,        -- Master division value, (1-56)
   REF_JITTER1 => 0.0,        -- Reference input jitter in UI, (0.000-0.999).
   STARTUP_WAIT => "FALSE"    -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
   -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
   CLKOUT0 => CLKOUT0,   -- 1-bit output: CLKOUT0
   CLKOUT1 => CLKOUT1,   -- 1-bit output: CLKOUT1
   CLKOUT2 => CLKOUT2,   -- 1-bit output: CLKOUT2
   CLKOUT3 => CLKOUT3,   -- 1-bit output: CLKOUT3
   CLKOUT4 => CLKOUT4,   -- 1-bit output: CLKOUT4
   CLKOUT5 => CLKOUT5,   -- 1-bit output: CLKOUT5
   -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
   CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock
   LOCKED => LOCKED,     -- 1-bit output: LOCK
   CLKIN1 => CLKIN1,     -- 1-bit input: Input clock
   -- Control Ports: 1-bit (each) input: PLL control ports
   PWRDWN => PWRDWN,     -- 1-bit input: Power-down
   RST => RST,           -- 1-bit input: Reset
   -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
   CLKFBIN => CLKFBIN    -- 1-bit input: Feedback clock
);

-- End of PLLE2_BASE_inst instantiation

Verilog Instantiation Template


// PLLE2_BASE: Base Phase Locked Loop (PLL)
//             7 Series
// Xilinx HDL Language Template, version 2022.1

PLLE2_BASE #(
   .BANDWIDTH("OPTIMIZED"),  // OPTIMIZED, HIGH, LOW
   .CLKFBOUT_MULT(5),        // Multiply value for all CLKOUT, (2-64)
   .CLKFBOUT_PHASE(0.0),     // Phase offset in degrees of CLKFB, (-360.000-360.000).
   .CLKIN1_PERIOD(0.0),      // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
   // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
   .CLKOUT0_DIVIDE(1),
   .CLKOUT1_DIVIDE(1),
   .CLKOUT2_DIVIDE(1),
   .CLKOUT3_DIVIDE(1),
   .CLKOUT4_DIVIDE(1),
   .CLKOUT5_DIVIDE(1),
   // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
   .CLKOUT0_DUTY_CYCLE(0.5),
   .CLKOUT1_DUTY_CYCLE(0.5),
   .CLKOUT2_DUTY_CYCLE(0.5),
   .CLKOUT3_DUTY_CYCLE(0.5),
   .CLKOUT4_DUTY_CYCLE(0.5),
   .CLKOUT5_DUTY_CYCLE(0.5),
   // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
   .CLKOUT0_PHASE(0.0),
   .CLKOUT1_PHASE(0.0),
   .CLKOUT2_PHASE(0.0),
   .CLKOUT3_PHASE(0.0),
   .CLKOUT4_PHASE(0.0),
   .CLKOUT5_PHASE(0.0),
   .DIVCLK_DIVIDE(1),        // Master division value, (1-56)
   .REF_JITTER1(0.0),        // Reference input jitter in UI, (0.000-0.999).
   .STARTUP_WAIT("FALSE")    // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
PLLE2_BASE_inst (
   // Clock Outputs: 1-bit (each) output: User configurable clock outputs
   .CLKOUT0(CLKOUT0),   // 1-bit output: CLKOUT0
   .CLKOUT1(CLKOUT1),   // 1-bit output: CLKOUT1
   .CLKOUT2(CLKOUT2),   // 1-bit output: CLKOUT2
   .CLKOUT3(CLKOUT3),   // 1-bit output: CLKOUT3
   .CLKOUT4(CLKOUT4),   // 1-bit output: CLKOUT4
   .CLKOUT5(CLKOUT5),   // 1-bit output: CLKOUT5
   // Feedback Clocks: 1-bit (each) output: Clock feedback ports
   .CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
   .LOCKED(LOCKED),     // 1-bit output: LOCK
   .CLKIN1(CLKIN1),     // 1-bit input: Input clock
   // Control Ports: 1-bit (each) input: PLL control ports
   .PWRDWN(PWRDWN),     // 1-bit input: Power-down
   .RST(RST),           // 1-bit input: Reset
   // Feedback Clocks: 1-bit (each) input: Clock feedback ports
   .CLKFBIN(CLKFBIN)    // 1-bit input: Feedback clock
);

// End of PLLE2_BASE_inst instantiation

Related Information

  • See the 7 Series FPGAs Clocking Resource User Guide (UG472).