BUFMRCE - 2022.1 English

Primitive: Multi-Region Clock Buffer with Clock Enable

Introduction

The BUFMRCE is a multi-region clock-in/clock-out buffer with clock with clock enable (CE). Deasserting CE stops the output clock to a user specified value. The BUFMRCE replaces the multi-region/bank support of the BUFR and BUFIO available in prior Virtex architectures. There are two BUFMRCEs in every bank and each buffer can be driven by one specific MRCC in the same bank. The BUFMRCE drives the BUFIOs and/or BUFRs in the same region/banks and in the region above and below via the I/O clocking backbone. When using BUFR dividers (not in bypass), the BUFMRCE must be disabled by deasserting the CE pin, the BUFR must be reset (cleared by asserting CLR), and then the CE signal should be asserted. This sequence ensures that all BUFR output clocks are phase aligned. If the dividers within the BUFRs are not used, then this additional circuitry is not necessary. If the clock enable circuitry is not needed, a BUFMR component should be used in place of a BUFMRCE.

Port Descriptions

Port	Direction	Width	Function
CE	Input	1	Active-High buffer enable input. When low, output will settle to INIT_OUT value.
I	Input	1	BUFMR clock input pin. Connect to an IBUF input that in turn is directly connected to a MRCC I/O port.
O	Output	1	BUFMR clock output pin. Connect to BUFIOs and/or BUFRs to be driven in the same and adjacent regions.

Design Entry Method

Instantiation	Yes
Inference	No
IP Catalog	No
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
CE_TYPE	STRING	"SYNC", "ASYNC"	"SYNC"	Set to "SYNC" for CE to be synchronous to input I and create a glitchless output. Set to "ASYNC" for stopped clock or non-clock operation of the CE signal.
INIT_OUT	DECIMAL	0, 1	0	Initial output value, also indicates stop low vs. stop high behavior

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- BUFMRCE: Multi-Region Clock Buffer with Clock Enable
--          7 Series
-- Xilinx HDL Language Template, version 2022.1

BUFMRCE_inst : BUFMRCE
generic map (
   CE_TYPE => "SYNC", -- SYNC, ASYNC
   INIT_OUT => 0      -- Initial output and stopped polarity, (0-1)
)
port map (
   O => O,   -- 1-bit output: Clock output (connect to BUFIOs/BUFRs)
   CE => CE, -- 1-bit input: Active high buffer enable
   I => I    -- 1-bit input: Clock input (Connect to IBUF)
);

-- End of BUFMRCE_inst instantiation

Verilog Instantiation Template


// BUFMRCE: Multi-Region Clock Buffer with Clock Enable
//          7 Series
// Xilinx HDL Language Template, version 2022.1

BUFMRCE #(
   .CE_TYPE("SYNC"), // SYNC, ASYNC
   .INIT_OUT(0)      // Initial output and stopped polarity, (0-1)
)
BUFMRCE_inst (
   .O(O),   // 1-bit output: Clock output (connect to BUFIOs/BUFRs)
   .CE(CE), // 1-bit input: Active high buffer enable
   .I(I)    // 1-bit input: Clock input (Connect to IBUF)
);

// End of BUFMRCE_inst instantiation

Related Information

See the 7 Series FPGAs Clocking Resource User Guide (UG472).