Macro: Adder/Subtracter
Introduction
ADDSUB_MACRO simplifies the instantiation of the DSP48 block when used as a simple adder/subtracter. It features parameterizable input and output widths and latency that ease the integration of the DSP48 block into HDL.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CARRYOUT | Output | 1 | Carry Out |
RESULT | Output | Variable, see WIDTH attribute. | Data output bus addressed by RDADDR. |
ADDSUB | Input | 1 | When high, RESULT is an addition. When low, RESULT is a subtraction. |
A | Input | Variable, see WIDTH attribute. | Data input to add/sub. |
B | Input | Variable, see WIDTH attribute. | Data input to add/sub. |
CE | Input | 1 | Clock Enable. |
CARRYIN | Input | 1 | Carry In. |
CLK | Input | 1 | Clock. |
RST | Input | 1 | Synchronous Reset. |
Design Entry Method
This unimacro is a parameterizable version of the primitive, and can be
instantiated only.
Instantiation | Yes |
Inference | No |
IP Catalog | No |
Macro support | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEVICE | STRING | "7SERIES" | "7SERIES" | Target hardware architecture. |
LATENCY | INTEGER | 0, 1, 2 | 2 | Number of pipeline registers.
|
WIDTH | INTEGER | 1-48 | 48 | Result port width override. |
VHDL Instantiation Template
Unless
they already exist, copy the following four statements and paste them
before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
-- ADDSUB_MACRO: Variable width & latency - Adder / Subtrator implemented in a DSP48E
-- 7 Series
-- Xilinx HDL Language Template, version 2022.1
ADDSUB_MACRO_inst : ADDSUB_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
LATENCY => 2, -- Desired clock cycle latency, 0-2
WIDTH => 48) -- Input / Output bus width, 1-48
port map (
CARRYOUT => CARRYOUT, -- 1-bit carry-out output signal
RESULT => RESULT, -- Add/sub result output, width defined by WIDTH generic
A => A, -- Input A bus, width defined by WIDTH generic
ADD_SUB => ADD_SUB, -- 1-bit add/sub input, high selects add, low selects subtract
B => B, -- Input B bus, width defined by WIDTH generic
CARRYIN => CARRYIN, -- 1-bit carry-in input
CE => CE, -- 1-bit clock enable input
CLK =>CLK, -- 1-bit clock input
RST => RST -- 1-bit active high synchronous reset
);
-- End of ADDSUB_MACRO_inst instantiation
Verilog Instantiation Template
// ADDSUB_MACRO: Variable width & latency - Adder / Subtracter implemented in a DSP48E
// 7 Series
// Xilinx HDL Language Template, version 2022.1
ADDSUB_MACRO #(
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.LATENCY(2), // Desired clock cycle latency, 0-2
.WIDTH(48) // Input / output bus width, 1-48
) ADDSUB_MACRO_inst (
.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal
.RESULT(RESULT), // Add/sub result output, width defined by WIDTH parameter
.A(A), // Input A bus, width defined by WIDTH parameter
.ADD_SUB(ADD_SUB), // 1-bit add/sub input, high selects add, low selects subtract
.B(B), // Input B bus, width defined by WIDTH parameter
.CARRYIN(CARRYIN), // 1-bit carry-in input
.CE(CE), // 1-bit clock enable input
.CLK(CLK), // 1-bit clock input
.RST(RST) // 1-bit active high synchronous reset
);
// End of ADDSUB_MACRO_inst instantiation