Primitive: 3-State Output Buffer with Differential Signaling,
Active-Low Output Enable
Introduction
This design element is an
output buffer that supports low-voltage, differential signaling.
For the OBUFTDS, a design level interface signal is represented as
two distinct ports (O and OB), one deemed the "master" and the other
the "slave." The master and the slave are opposite phases of the same
logical signal (for example, MYNET_P and MYNET_N).
Logic Table
| Inputs |
Outputs |
| I |
T |
O |
OB |
| X |
1 |
Z |
Z |
| 0 |
0 |
0 |
1 |
| 1 |
0 |
1 |
0 |
Port Descriptions
| Port |
Direction |
Width |
Function |
| O |
Output |
1 |
Diff_p output (connect directly to top level port). |
| OB |
Output |
1 |
Diff_n output (connect directly to top level port). |
| I |
Input |
1 |
Buffer input. |
| T |
Input |
1 |
3-state enable input. |
Design Entry Method
| Instantiation |
Recommended |
| Inference |
No |
| IP Catalog |
No |
| Macro support |
No |
Available Attributes
| Attribute |
Type |
Allowed Values |
Default |
Description |
| IOSTANDARD |
STRING |
See Data Sheet |
"DEFAULT" |
Assigns an I/O standard to the element. |
| SLEW |
STRING |
"SLOW" or "FAST" |
"SLOW" |
Specifies the slew rate of the output driver. Consult the product
Data Sheet for recommendations of the best setting for this attribute. |
VHDL
Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFTDS: Differential 3-state Output Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2022.1
OBUFTDS_inst : OBUFTDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Diff_p output (connect directly to top-level port)
OB => OB, -- Diff_n output (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input
);
-- End of OBUFTDS_inst instantiation
Verilog
Instantiation Template
// OBUFTDS: Differential 3-state Output Buffer
// 7 Series
// Xilinx HDL Language Template, version 2022.1
OBUFTDS #(
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUFTDS_inst (
.O(O), // Diff_p output (connect directly to top-level port)
.OB(OB), // Diff_n output (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input
);
// End of OBUFTDS_inst instantiation
