IOBUF - 2022.1 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2022-04-20
Version
2022.1 English

Primitive: Bi-Directional Buffer

Introduction

The design element is a bidirectional single-ended I/O Buffer used to connect internal logic to an external bidirectional pin.

Logic Table

Inputs Bidirectional Outputs
T I IO O
1 X Z IO
0 1 1 1
0 0 0 0

Port Descriptions

Port Direction Width Function
O Output 1 Buffer output.
IO In/out 1 Buffer In/out..
I Input 1 Buffer input.
T Input 1 3-State enable input.

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
DRIVE INTEGER 2, 4, 6, 8, 12, 16, 24 12 Selects output drive strength (mA) for the SelectIO™ buffers that use the LVTTL, LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, or LVCMOS33 interface I/O standard.
IOSTANDARD STRING See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
SLEW STRING "SLOW", "FAST" "SLOW" Sets the output rise and fall time.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IOBUF: Single-ended Bi-directional Buffer
--        7 Series
-- Xilinx HDL Language Template, version 2022.1

IOBUF_inst : IOBUF
generic map (
   DRIVE => 12,
   IOSTANDARD => "DEFAULT",
   SLEW => "SLOW")
port map (
   O => O,     -- Buffer output
   IO => IO,   -- Buffer inout port (connect directly to top-level port)
   I => I,     -- Buffer input
   T => T      -- 3-state enable input, high=input, low=output
);

-- End of IOBUF_inst instantiation

Verilog Instantiation Template


// IOBUF: Single-ended Bi-directional Buffer
//        All devices
// Xilinx HDL Language Template, version 2022.1

IOBUF #(
   .DRIVE(12), // Specify the output drive strength
   .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE"
   .IOSTANDARD("DEFAULT"), // Specify the I/O standard
   .SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
   .O(O),     // Buffer output
   .IO(IO),   // Buffer inout port (connect directly to top-level port)
   .I(I),     // Buffer input
   .T(T)      // 3-state enable input, high=input, low=output
);

// End of IOBUF_inst instantiation

Related Information

  • See the 7 Series FPGA SelectIO Resources User Guide (UG471).