Primitive: HROW Clock Buffer for a Single Clocking Region
Introduction
The BUFH primitive allows direct access to the clock region entry point of the global buffer (BUFG) resource. This allows access to unused portions of the global clocking network to be used as high-speed, low skew local (single clock region) routing resources.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Clock input. |
| O | Output | 1 | Clock output. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP Catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFH: HROW Clock Buffer for a Single Clocking Region
-- 7 Series
-- Xilinx HDL Language Template, version 2022.1
BUFH_inst : BUFH
port map (
O => O, -- 1-bit output: Clock output
I => I -- 1-bit input: Clock input
);
-- End of BUFH_inst instantiation
Verilog Instantiation Template
// BUFH: HROW Clock Buffer for a Single Clocking Region
// 7 Series
// Xilinx HDL Language Template, version 2022.1
BUFH BUFH_inst (
.O(O), // 1-bit output: Clock output
.I(I) // 1-bit input: Clock input
);
// End of BUFH_inst instantiation
Related Information
- See the 7 Series FPGAs Clocking Resource User Guide (UG472).