Primitive: Output Fixed or Variable Delay Element
Introduction
This design element can be used to provide a fixed delay or an adjustable delay to
the output path of the 7 series FPGA. This delay can be useful for the purpose of
external data alignment, external phase offset and simultaneous switching noise
(SSN) mitigation, as well as allowing for the tracking of external data alignment
over process, temperature, and voltage (PVT). When used with the IDELAYCTRL
component circuitry, can provide precise time increments of delay. When used in
variable mode, the output path can be adjusted for increasing and decreasing amounts
of delay. The ODELAYE2 is not available on the High Range (HR) banks in the 7 series
devices.
Port Descriptions
Port |
Direction |
Width |
Function |
C |
Input |
1 |
All control inputs to ODELAYE2 primitive (CNTVALUEIN, RST,
CE, LD, LDPIPEEN and INC) are synchronous to the clock input (C).
A clock must be connected to this port when the ODELAYE2 is configured
in "VARIABLE", "VAR_LOAD" or "VAR_LOAD_PIPE" mode. C can be locally
inverted, and must be supplied by a global or regional clock buffer.
This clock should be connected to the same clock in the SelectIO logic
resources (when using OSERDESE2, C is connected to CLKDIV). If the
ODELAYE2 is configured as "FIXED", connect this port to gnd. |
CE |
Input |
1 |
Active-High enable increment/decrement function. If the ODELAYE2 is
configured as "FIXED", connect this port to gnd. |
CINVCTRL |
Input |
1 |
The CINVCTRL pin is used for dynamically switching the polarity
of C pin. This is for use in applications when glitches are not an
issue. When switching the polarity, do not use the ODELAYE2 control
pins for two clock cycles. If the ODELAYE2 is configured as "FIXED",
connect this port to gnd. |
CLKIN |
Input |
1 |
Delayed Clock input into the ODELAYE2. |
CNTVALUEIN<4:0> |
Input |
5 |
Counter value from FPGA logic for dynamically loadable tap value input when
configured in "VAR_LOAD" or "VAR_LOAD_PIPE" modes. If the ODELAYE2
is configured as "FIXED" or "VARIABLE", connect this port to gnd. |
CNTVALUEOUT<4:0> |
Output |
5 |
The CNTVALUEOUT pins are used for reporting the dynamically
switching value of the delay element. CNTVALUEOUT is only available
when ODELAYE2 is in "VAR_LOAD" or "VAR_LOAD_PIPE" mode. |
DATAOUT |
Output |
1 |
Delayed data/clock from either the CLKIN or ODATAIN ports.
DATAOUT connects to an I/O port in the case of data or back to the
clocking structure in the case of a clock.. |
INC |
Input |
1 |
The increment/decrement is controlled by the enable signal
(CE). This interface is only available when ODELAYE2 is in VARIABLE,
VAR_LOAD, or VAR_LOAD_PIPE mode. |
LD |
Input |
1 |
Load initial value or loaded value to the counter. |
LDPIPEEN |
Input |
1 |
Enable PIPELINE register to load data from LD pins. |
ODATAIN |
Input |
1 |
The ODATAIN input is the output data to be delayed driven by
the OSERDESE2 or output register. |
REGRST |
Input |
1 |
The REGRST signal is an active-High reset and is synchronous to the input
clock signal (C). When asserted, the tap value reverts to a zero
state unless LDPIPEEN is also asserted in which case the tap value
results in the value on the CNTVALUEIN port. |
Design Entry Method
Instantiation |
Yes |
Inference |
No |
IP Catalog |
Yes |
Macro support |
No |
Available Attributes
Attribute |
Type |
Allowed Values |
Default |
Description |
CINVCTRL_SEL |
STRING |
"FALSE", "TRUE" |
"FALSE" |
Enables the CINVCTRL_SEL pin to dynamically switch the polarity
of the C pin. |
DELAY_SRC |
STRING |
"ODATAIN", "CLKIN" |
"ODATAIN" |
Select the data input source:
- "ODATAIN": ODELAYE2 chain input is ODATAIN
- "CLKIN": ODELAYE2 chain input is CLKIN
|
HIGH _PERFORMANCE _MODE |
STRING |
"FALSE", "TRUE" |
"FALSE" |
When TRUE, this attribute reduces the output jitter. When FALSE,
power consumption is reduced. The difference in power consumption
is quantified in the Xilinx Power Estimator tool. |
ODELAY_TYPE |
STRING |
"FIXED", "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" |
"FIXED" |
Sets the type of tap delay line.
- "FIXED": Sets a static delay value
- "VARIABLE": Dynamically adjust (increment/decrement) delay value
- "VAR_LOAD": Dynamically loads tap values
- "VAR_LOAD_PIPE": Pipelined dynamically loadable tap values
|
ODELAY_VALUE |
DECIMAL |
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 |
0 |
Specifies the fixed number of delay taps in fixed mode or the
initial starting number of taps in "VARIABLE" mode (output path).
When IDELAY_TYPE is set to "VAR_LOAD" or "VAR_LOAD_PIPE" mode, this
value is ignored. |
PIPE_SEL |
STRING |
"FALSE", "TRUE" |
"FALSE" |
Select pipelined mode. |
REFCLK _FREQUENCY |
1 significant digit FLOAT |
190-210, 290-310 Mhz |
200.0 |
Sets the tap value (in Mhz) used by the Timing Analyzer for static timing
analysis and functional/timing simulation. The frequency of REFCLK
must be within the given datasheet range to guarantee the tap-delay
value and performance. |
SIGNAL_PATTERN |
STRING |
"DATA", "CLOCK" |
"DATA" |
Causes timing analysis to account for the appropriate amount
of delay-chain jitter when presented with either a "DATA" pattern
with irregular transitions or a "CLOCK" pattern with a regular rise/fall
pattern. |
VHDL
Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ODELAYE2: Output Fixed or Variable Delay Element
-- 7 Series
-- Xilinx HDL Language Template, version 2022.1
ODELAYE2_inst : ODELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE)
DELAY_SRC => "ODATAIN", -- Delay input (ODATAIN, CLKIN)
HIGH_PERFORMANCE_MODE => "FALSE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
ODELAY_TYPE => "FIXED", -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
ODELAY_VALUE => 0, -- Output delay tap setting (0-31)
PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE
REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
SIGNAL_PATTERN => "DATA" -- DATA, CLOCK input signal
)
port map (
CNTVALUEOUT => CNTVALUEOUT, -- 5-bit output: Counter value output
DATAOUT => DATAOUT, -- 1-bit output: Delayed data/clock output
C => C, -- 1-bit input: Clock input
CE => CE, -- 1-bit input: Active high enable increment/decrement input
CINVCTRL => CINVCTRL, -- 1-bit input: Dynamic clock inversion input
CLKIN => CLKIN, -- 1-bit input: Clock delay input
CNTVALUEIN => CNTVALUEIN, -- 5-bit input: Counter value input
INC => INC, -- 1-bit input: Increment / Decrement tap delay input
LD => LD, -- 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
-- VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
LDPIPEEN => LDPIPEEN, -- 1-bit input: Enables the pipeline register to load data
ODATAIN => ODATAIN, -- 1-bit input: Output delay data input
REGRST => REGRST -- 1-bit input: Active-high reset tap-delay input
);
-- End of ODELAYE2_inst instantiation
Verilog
Instantiation Template
// ODELAYE2: Output Fixed or Variable Delay Element
// 7 Series
// Xilinx HDL Language Template, version 2022.1
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
ODELAYE2 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.ODELAY_VALUE(0), // Output delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
ODELAYE2_inst (
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
.DATAOUT(DATAOUT), // 1-bit output: Delayed data/clock output
.C(C), // 1-bit input: Clock input
.CE(CE), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(CINVCTRL), // 1-bit input: Dynamic clock inversion input
.CLKIN(CLKIN), // 1-bit input: Clock delay input
.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
.INC(INC), // 1-bit input: Increment / Decrement tap delay input
.LD(LD), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
// VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
.LDPIPEEN(LDPIPEEN), // 1-bit input: Enables the pipeline register to load data
.ODATAIN(ODATAIN), // 1-bit input: Output delay data input
.REGRST(REGRST) // 1-bit input: Active-high reset tap-delay input
);
// End of ODELAYE2_inst instantiation