Primitive: Global Clock Simple Buffer
Introduction
This design element is a high-fanout buffer that connects signals to the global routing resources for low skew distribution of the signal. BUFGs are typically used on clock nets as well other high fanout nets like sets/resets and clock enables.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Clock input. |
| O | Output | 1 | Clock output. |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP Catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFG: Global Clock Simple Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2022.1
BUFG_inst : BUFG
port map (
O => O, -- 1-bit output: Clock output
I => I -- 1-bit input: Clock input
);
-- End of BUFG_inst instantiation
Verilog Instantiation Template
// BUFG: Global Clock Simple Buffer
// 7 Series
// Xilinx HDL Language Template, version 2022.1
BUFG BUFG_inst (
.O(O), // 1-bit output: Clock output
.I(I) // 1-bit input: Clock input
);
// End of BUFG_inst instantiation
Related Information
- See the 7 Series FPGAs Clocking Resource User Guide (UG472).