Primitive: Single-ended Input Buffer with Input Disable
Introduction
This design element is an input buffer used to connect internal logic to an external pin. This element includes an input path disable as an additional power saving feature when the I/O is not used for a sustained amount of time.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
I | Input | 1 | Input port connection. Connect directly to top-level port in the design. |
IBUFDISABLE | Input | 1 | Disables input path through the buffer and forces to a logic high when USE_IBUFDISABLE is set to "TRUE" and this signal is asserted high. If USE_IBUFDISABLE is set to "FALSE" this input is ignored and should be tied to ground. This feature is generally used to reduce power at times when the I/O is idle for a period of time. |
O | Output | 1 | Buffer output representing the input path to the device. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP Catalog | Yes |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
IBUF_LOW_PWR | STRING | "TRUE", "FALSE" | "TRUE" | Allows a trade off of lower power consumption versus highest performance when referenced I/O standards are used. |
IOSTANDARD | STRING | See Data Sheet | "DEFAULT" | Assigns an I/O standard to the element. |
USE_IBUFDISABLE | STRING | "TRUE", "FALSE" | "TRUE" | Enables or disables the feature of IBUFDISABLE. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUF_IBUFDISABLE: Single-ended Input Buffer with Disable
-- 7 Series
-- Xilinx HDL Language Template, version 2022.1
IBUF_IBUFDISABLE_inst : IBUF_IBUFDISABLE
generic map (
IBUF_LOW_PWR => "TRUE", -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT", -- Specify the input I/O standard
USE_IBUFDISABLE => "TRUE") -- Set to "TRUE" to enable IBUFDISABLE feature
port map (
O => O, -- Buffer output
I => I, -- Buffer input (connect directly to top-level port)
IBUFDISABLE => IBUFDISABLE -- Buffer disable input, low=disable
);
-- End of IBUF_IBUFDISABLE_inst instantiation
Verilog Instantiation Template
// IBUF_IBUFDISABLE: Single-ended Input Buffer with Disable
// 7 Series
// Xilinx HDL Language Template, version 2022.1
IBUF_IBUFDISABLE #(
.IBUF_LOW_PWR("TRUE"), // Low power ("TRUE") vs. performance ("FALSE") for referenced I/O standards
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
) IBUF_IBUFDISABLE_inst (
.O(O), // Buffer output
.I(I), // Buffer input (connect directly to top-level port)
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, high=disable
);
// End of IBUF_IBUFDISABLE_inst instantiation
Related Information
- See the 7 Series FPGA SelectIO Resources User Guide (UG471).