IBUFDS_INTERMDISABLE - 2022.1 English

Primitive: Input Differential Buffer with Input Termination Disable and Input Disable

Introduction

This design element is an input differential buffer used to connect internal logic to an external bidirectional pin. This element includes an uncalibrated input termination (INTERM) disable as well as input path disable as additional power saving features when the input is idle for a sustained amount of time. This element may only be placed in High Range (HR) banks in the 7 series devices.

Port Descriptions

Port	Direction	Width	Function
I	Input	1	Input p-side port connection. Connect directly to a top-level port in the design.
IB	Input	1	Input n-side port connection. Connect directly to a top-level port in the design.
IBUFDISABLE	Input	1	Disables input path through the buffer and forces to a logic High when USE_IBUFDISABLE is set to "TRUE" and this signal is asserted High. If USE_IBUFDISABLE is set to "FALSE" this input is ignored and should be tied to ground. This feature is generally used to reduce power at times when the I/O is idle.
INTERMDISABLE	Input	1	Disables input termination. This feature is generally used to reduce power at times when the I/O is idle.
O	Output	1	Buffer output representing the input path to the device.

Design Entry Method

Instantiation	Yes
Inference	No
IP Catalog	Yes
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
DIFF_TERM	STRING	"TRUE", "FALSE"	"FALSE"	Turns the built-in differential termination on (TRUE) or off (FALSE).
IBUF_LOW_PWR	STRING	"TRUE", "FALSE"	"TRUE"	Allows a trade off of lower power consumption versus. highest performance when referenced I/O standards are used.
IOSTANDARD	STRING	See Data Sheet	"DEFAULT"	Assigns an I/O standard to the element.
USE_IBUFDISABLE	STRING	"TRUE", "FALSE"	"TRUE"	Enables or disables the IBUFDISABLE feature. Generally used when it is not desirable to disable the input path in order to allow a read during write operation.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IBUFDS_INTERMDISABLE: Differential Input Buffer with Input Termination Disable
--                       May only be placed in High Range (HR) Banks
--                       7 Series
-- Xilinx HDL Language Template, version 2022.1

IBUFDS_INTERMDISABLE_inst : IBUFDS_INTERMDISABLE
generic map (
   DIFF_TERM => "FALSE", -- Differential Termination
   IBUF_LOW_PWR => "TRUE", -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD => "DEFAULT", -- Specify the input I/O standard
   USE_IBUFDISABLE => "TRUE") -- Set to "TRUE" to enable IBUFDISABLE feature
port map (
   O => O,  -- Buffer output
   I => I,  -- Diff_p buffer input (connect directly to top-level port)
   IB => IB, -- Diff_n buffer input (connect directly to top-level port)
   IBUFDISABLE => IBUFDISABLE, -- Buffer disable input, low=disable
   INTERMDIBSALE => INTERMDISABLE -- Input termination disable
);

-- End of IBUFDS_IBUFDISABLE_inst instantiation

Verilog Instantiation Template


// IBUFDS_INTERMDISABLE: Differential Input Buffer with Input Termination Disable
//                       May only be placed in High Range (HR) Banks
//                       7 Series
// Xilinx HDL Language Template, version 2022.1

IBUFDS_INTERMDISABLE #(
   .DIFF_TERM("FALSE"),      // Differential Termination
   .IBUF_LOW_PWR("TRUE"),    // Low power="TRUE", Highest performance="FALSE"
   .IOSTANDARD("DEFAULT"),   // Specify the input I/O standard
   .USE_IBUFDISABLE("TRUE")  // Set to "TRUE" to enable IBUFDISABLE feature
) IBUFDS_INTERMDISABLE_inst (
   .O(O),   // Buffer output
   .I(I),   // Diff_p buffer input (connect directly to top-level port)
   .IB(IB), // Diff_n buffer input (connect directly to top-level port)
   .IBUFDISABLE(IBUFDISABLE),    // Buffer disable input, high=disable
   .INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
);

// End of IBUFDS_INTERMDISABLE_inst instantiation

Related Information

See the 7 Series FPGA SelectIO Resources User Guide (UG471).