XADC - 2022.1 English

Primitive: Dual 12-Bit 1MSPS Analog-to-Digital Converter

Introduction

XADC includes a dual 12-bit, 1 Mega sample per second (MSPS) ADC and on-chip sensors. These ADCs are fully tested and specified (see the respective 7 series FPGAs data sheet). The ADCs provide a general-purpose, high-precision analog interface for a range of applications. The dual ADCs support a range of operating modes, for example, externally triggered and simultaneous sampling on both ADCs and various analog input signal types, for example, unipolar, and differential. The ADCs can access up to 17 external analog input channels.

XADC also includes a number of on-chip sensors that support measurement of the on-chip power supply voltages and die temperature. The ADC conversion data is stored in dedicated registers called status registers. These registers are accessible via the FPGA interconnect using a 16-bit synchronous read and write port called the Dynamic Reconfiguration Port (DRP). ADC conversion data is also accessible via the JTAG TAP. In the latter case, users are not required to instantiate the XADC because it is a dedicated interface that uses the existing FPGA JTAG infrastructure. If the XADC is not instantiated in a design, the device operates in a predefined mode (called default mode) that monitors on-chip temperature and supply voltages.

XADC operation is user defined by writing to the control registers using either the DRP or JTAG interface. It is also possible to initialize these register contents when the XADC is instantiated in a design using the block attributes.

Port Descriptions

Port	Direction	Width	Function
ALM<7:0>	Output	8	Output alarm for temperature, Vccint, Vccaux and Vccbram. ALM[0]: XADC temperature sensor alarm output. ALM[1]: XADC Vccint sensor alarm output. ALM[2]: XADC Vccaux sensor alarm output. ALM[3]: XADC Vccbram sensor alarm output. ALM[6:4]: Not defined.
BUSY	Output	1	ADC busy signal. This signal transitions High during an ADC conversion. This signal also transitions High for an extended period during an ADC or sensor calibration.
CHANNEL<4:0>	Output	5	Channel selection outputs. The ADC input MUX channel selection for the current ADC conversion is placed on these outputs at the end of an ADC conversion.
CONVST	Input	1	Convert start input. This input controls the sampling instant on the ADC(s) input and is only used in event mode timing. This input comes from the general-purpose interconnect in the FPGA logic.
CONVSTCLK	Input	1	Convert start clock input. This input is connected to a clock net. Like CONVST, this input controls the sampling instant on the ADC(s) inputs and is only used in event mode timing. This input comes from the local clock distribution network in the FPGA logic. Thus, for the best control over the sampling instant (delay and jitter), a global clock input can be used as the CONVST source.
DADDR<6:0>	Input	7	Address bus for the dynamic reconfiguration port.
DCLK	Input	1	Clock input for the dynamic reconfiguration port.
DEN	Input	1	Enable signal for the dynamic reconfiguration port.
DI<15:0>	Input	16	Input data bus for the dynamic reconfiguration port.
DO<15:0>	Output	16	Output data bus for dynamic reconfiguration port.
DRDY	Output	1	Data ready signal for the dynamic reconfiguration port.
DWE	Input	1	Write enable for the dynamic reconfiguration port.
EOC	Output	1	End of Conversion signal. This signal transitions to an active High at the end of an ADC conversion when the measurement is written to the status registers.
EOS	Output	1	End of Sequence. This signal transitions to active-High when the measurement data from the last channel in an automatic channel sequence is written to the status registers.
JTAGBUSY	Output	1	Used to indicate that a JTAG DRP transaction is in progress.
JTAGLOCKED	Output	1	Indicates that a DRP port lock request has been made by the JTAG interface. This signal is also used to indicate that the DRP is ready for access (when Low).
JTAGMODIFIED	Output	1	Used to indicate that a JTAG Write to the DRP has occurred.
MUXADDR<4:0>	Output	5	These outputs are used in external multiplexer mode. They indicate the address of the next channel in a sequence to be converted. They provide the channel address for an external multiplexer.
OT	Output	1	Over-Temperature alarm
RESET	Input	1	Reset signal for the XADC control logic.
VAUXN<15:0>	Input	16	N-side auxiliary analog input
VAUXP<15:0>	Input	16	P-side auxiliary analog input
VN	Input	1	N-side analog input
VP	Input	1	P-side analog input

Design Entry Method

Instantiation	Yes
Inference	No
IP Catalog	Recommended
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
INIT_4A	HEX	16'h0000 to 16'hffff	16'h0000	Sequence register 2
INIT_4B	HEX	16'h0000 to 16'hffff	16'h0000	Sequence register 3
INIT_4C	HEX	16'h0000 to 16'hffff	16'h0000	Sequence register 4
INIT_4D	HEX	16'h0000 to 16'hffff	16'h0000	Sequence register 5
INIT_4E	HEX	16'h0000 to 16'hffff	16'h0000	Sequence register 6
INIT_4F	HEX	16'h0000 to 16'hffff	16'h0000	Sequence register 7
INIT_5C	HEX	16'h0000 to 16'hffff	16'h0000	Vbram lower alarm threshold
INIT_40	HEX	16'h0000 to 16'hffff	16'h0000	Configuration register 0
INIT_41	HEX	16'h0000 to 16'hffff	16'h0000	Configuration register 1
INIT_42	HEX	16'h0000 to 16'hffff	16'h0800	Configuration register 2
INIT_43	HEX	16'h0000 to 16'hffff	16'h0000	Test register 0
INIT_44	HEX	16'h0000 to 16'hffff	16'h0000	Test register 1
INIT_45	HEX	16'h0000 to 16'hffff	16'h0000	Test register 2
INIT_46	HEX	16'h0000 to 16'hffff	16'h0000	Test register 3
INIT_47	HEX	16'h0000 to 16'hffff	16'h0000	Test register 4
INIT_48	HEX	16'h0000 to 16'hffff	16'h0000	Sequence register 0
INIT_49	HEX	16'h0000 to 16'hffff	16'h0000	Sequence register 1
INIT_50	HEX	16'h0000 to 16'hffff	16'h0000	Alarm limit register 0
INIT_51	HEX	16'h0000 to 16'hffff	16'h0000	Alarm limit register 1
INIT_52	HEX	16'h0000 to 16'hffff	16'h0000	Alarm limit register 2
INIT_53	HEX	16'h0000 to 16'hffff	16'h0000	Alarm limit register 3
INIT_54	HEX	16'h0000 to 16'hffff	16'h0000	Alarm limit register 4
INIT_55	HEX	16'h0000 to 16'hffff	16'h0000	Alarm limit register 5
INIT_56	HEX	16'h0000 to 16'hffff	16'h0000	Alarm limit register 6
INIT_57	HEX	16'h0000 to 16'hffff	16'h0000	Alarm limit register 7
INIT_58	HEX	16'h0000 to 16'hffff	16'h0000	Vbram upper alarm threshold
INIT_59, INIT_5A, INIT_5B, INIT_5D, INIT_5E, INIT_5F	HEX	16'h0000 to 16'hffff	16'h0000	Reserved for future use
SIM_DEVICE	STRING	"7SERIES", "ZYNQ"	"7SERIES"	Selects target device to allow for proper simulation.
SIM_MONITOR _FILE	STRING	String representing file name and location	"design.txt"	Specify the file name (and directory if different from simulation directory) of file containing analog voltage and temperature data for XADC simulation behavior.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
--       7 Series
-- Xilinx HDL Language Template, version 2022.1

XADC_inst : XADC
generic map (
   -- INIT_40 - INIT_42: XADC configuration registers
   INIT_40 => X"0000",
   INIT_41 => X"0000",
   INIT_42 => X"0800",
   -- INIT_48 - INIT_4F: Sequence Registers
   INIT_48 => X"0000",
   INIT_49 => X"0000",
   INIT_4A => X"0000",
   INIT_4B => X"0000",
   INIT_4C => X"0000",
   INIT_4D => X"0000",
   INIT_4F => X"0000",
   INIT_4E => X"0000",                 -- Sequence register 6
   -- INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
   INIT_50 => X"0000",
   INIT_51 => X"0000",
   INIT_52 => X"0000",
   INIT_53 => X"0000",
   INIT_54 => X"0000",
   INIT_55 => X"0000",
   INIT_56 => X"0000",
   INIT_57 => X"0000",
   INIT_58 => X"0000",
   INIT_5C => X"0000",
   -- Simulation attributes: Set for proper simulation behavior
   SIM_DEVICE => "7SERIES",            -- Select target device (values)
   SIM_MONITOR_FILE => "design.txt"  -- Analog simulation data file name
)
port map (
   -- ALARMS: 8-bit (each) output: ALM, OT
   ALM => ALM,                   -- 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
   OT => OT,                     -- 1-bit output: Over-Temperature alarm
   -- Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
   DO => DO,                     -- 16-bit output: DRP output data bus
   DRDY => DRDY,                 -- 1-bit output: DRP data ready
   -- STATUS: 1-bit (each) output: XADC status ports
   BUSY => BUSY,                 -- 1-bit output: ADC busy output
   CHANNEL => CHANNEL,           -- 5-bit output: Channel selection outputs
   EOC => EOC,                   -- 1-bit output: End of Conversion
   EOS => EOS,                   -- 1-bit output: End of Sequence
   JTAGBUSY => JTAGBUSY,         -- 1-bit output: JTAG DRP transaction in progress output
   JTAGLOCKED => JTAGLOCKED,     -- 1-bit output: JTAG requested DRP port lock
   JTAGMODIFIED => JTAGMODIFIED, -- 1-bit output: JTAG Write to the DRP has occurred
   MUXADDR => MUXADDR,           -- 5-bit output: External MUX channel decode
   -- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
   VAUXN => VAUXN,               -- 16-bit input: N-side auxiliary analog input
   VAUXP => VAUXP,               -- 16-bit input: P-side auxiliary analog input
   -- CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
   CONVST => CONVST,             -- 1-bit input: Convert start input
   CONVSTCLK => CONVSTCLK,       -- 1-bit input: Convert start input
   RESET => RESET,               -- 1-bit input: Active-high reset
   -- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
   VN => VN,                     -- 1-bit input: N-side analog input
   VP => VP,                     -- 1-bit input: P-side analog input
   -- Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
   DADDR => DADDR,               -- 7-bit input: DRP address bus
   DCLK => DCLK,                 -- 1-bit input: DRP clock
   DEN => DEN,                   -- 1-bit input: DRP enable signal
   DI => DI,                     -- 16-bit input: DRP input data bus
   DWE => DWE                    -- 1-bit input: DRP write enable
);

-- End of XADC_inst instantiation

Verilog Instantiation Template


// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
//       7 Series
// Xilinx HDL Language Template, version 2022.1

XADC #(
   // INIT_40 - INIT_42: XADC configuration registers
   .INIT_40(16'h0000),
   .INIT_41(16'h0000),
   .INIT_42(16'h0800),
   // INIT_48 - INIT_4F: Sequence Registers
   .INIT_48(16'h0000),
   .INIT_49(16'h0000),
   .INIT_4A(16'h0000),
   .INIT_4B(16'h0000),
   .INIT_4C(16'h0000),
   .INIT_4D(16'h0000),
   .INIT_4F(16'h0000),
   .INIT_4E(16'h0000),                // Sequence register 6
   // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
   .INIT_50(16'h0000),
   .INIT_51(16'h0000),
   .INIT_52(16'h0000),
   .INIT_53(16'h0000),
   .INIT_54(16'h0000),
   .INIT_55(16'h0000),
   .INIT_56(16'h0000),
   .INIT_57(16'h0000),
   .INIT_58(16'h0000),
   .INIT_5C(16'h0000),
   // Simulation attributes: Set for proper simulation behavior
   .SIM_DEVICE("7SERIES"),            // Select target device (values)
   .SIM_MONITOR_FILE("design.txt")  // Analog simulation data file name
)
XADC_inst (
   // ALARMS: 8-bit (each) output: ALM, OT
   .ALM(ALM),                   // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
   .OT(OT),                     // 1-bit output: Over-Temperature alarm
   // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
   .DO(DO),                     // 16-bit output: DRP output data bus
   .DRDY(DRDY),                 // 1-bit output: DRP data ready
   // STATUS: 1-bit (each) output: XADC status ports
   .BUSY(BUSY),                 // 1-bit output: ADC busy output
   .CHANNEL(CHANNEL),           // 5-bit output: Channel selection outputs
   .EOC(EOC),                   // 1-bit output: End of Conversion
   .EOS(EOS),                   // 1-bit output: End of Sequence
   .JTAGBUSY(JTAGBUSY),         // 1-bit output: JTAG DRP transaction in progress output
   .JTAGLOCKED(JTAGLOCKED),     // 1-bit output: JTAG requested DRP port lock
   .JTAGMODIFIED(JTAGMODIFIED), // 1-bit output: JTAG Write to the DRP has occurred
   .MUXADDR(MUXADDR),           // 5-bit output: External MUX channel decode
   // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
   .VAUXN(VAUXN),               // 16-bit input: N-side auxiliary analog input
   .VAUXP(VAUXP),               // 16-bit input: P-side auxiliary analog input
   // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
   .CONVST(CONVST),             // 1-bit input: Convert start input
   .CONVSTCLK(CONVSTCLK),       // 1-bit input: Convert start input
   .RESET(RESET),               // 1-bit input: Active-high reset
   // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
   .VN(VN),                     // 1-bit input: N-side analog input
   .VP(VP),                     // 1-bit input: P-side analog input
   // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
   .DADDR(DADDR),               // 7-bit input: DRP address bus
   .DCLK(DCLK),                 // 1-bit input: DRP clock
   .DEN(DEN),                   // 1-bit input: DRP enable signal
   .DI(DI),                     // 16-bit input: DRP input data bus
   .DWE(DWE)                    // 1-bit input: DRP write enable
);

// End of XADC_inst instantiation

Related Information

See the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480).