Primitive: Fast Carry Logic with Look Ahead
Introduction
This circuit design represents the fast carry logic for a slice. The carry chain consists of a series of four MUXes and four XORs that connect to the other logic (LUTs) in the slice via dedicated routes to form more complex functions. The fast carry logic is useful for building arithmetic functions like adders, counters, subtracters and add/subs, as well as such other logic functions as wide comparators, address decoders, and some logic gates (specifically, AND and OR).
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| O | Output | 4 | Carry chain XOR general data out. |
| CO | Output | 4 | Carry-out of each stage of the carry chain. |
| DI | Input | 4 | Carry-MUX data input. |
| S | Input | 4 | Carry-MUX select line. |
| CYINIT | Input | 1 | Carry-in initialization input. |
| CI | Input | 1 | Carry cascade input. |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP Catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- CARRY4: Fast Carry Logic Component
-- 7 Series
-- Xilinx HDL Language Template, version 2022.1
CARRY4_inst : CARRY4
port map (
CO => CO, -- 4-bit carry out
O => O, -- 4-bit carry chain XOR data out
CI => CI, -- 1-bit carry cascade input
CYINIT => CYINIT, -- 1-bit carry initialization
DI => DI, -- 4-bit carry-MUX data in
S => S -- 4-bit carry-MUX select input
);
-- End of CARRY4_inst instantiation
Verilog Instantiation Template
// CARRY4: Fast Carry Logic Component
// 7 Series
// Xilinx HDL Language Template, version 2022.1
CARRY4 CARRY4_inst (
.CO(CO), // 4-bit carry out
.O(O), // 4-bit carry chain XOR data out
.CI(CI), // 1-bit carry cascade input
.CYINIT(CYINIT), // 1-bit carry initialization
.DI(DI), // 4-bit carry-MUX data in
.S(S) // 4-bit carry-MUX select input
);
// End of CARRY4_inst instantiation
Related Information
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).