Primitive: Global Clock Mux Buffer
Introduction
This design element is a global clock buffer, based on BUFGCTRL, that can select between two input clocks: I0 and I1. When the select input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal on I1 is selected for output. BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes when it switches between clocks in response to a change in the select input. BUFGMUX assumes output state 0 and BUFGMUX_1 assumes output state 1.
Logic Table
| Inputs | Outputs | ||
|---|---|---|---|
| I0 | I1 | S | O |
| I0 | X | 0 | I0 |
| X | I1 | 1 | I1 |
| X | X | ↑ | 0 |
| X | X | ↓ | 0 |
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I0 | Input | 1 | Clock buffer input. This input is reflected on the output O when the S input is zero. |
| I1 | Input | 1 | Clock buffer input. This input is reflected on the output O when the S input is one. |
| O | Output | 1 | Clock buffer output. |
| S | Input | 1 | Clock buffer select input. Selects the I0 input when Low and the I1 input when High. |
Design Entry Method
| Instantiation | Recommended |
| Inference | No |
| IP Catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGMUX: Global Clock Mux Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2022.1
BUFGMUX_inst : BUFGMUX
port map (
O => O, -- 1-bit output: Clock output
I0 => I0, -- 1-bit input: Clock input (S=0)
I1 => I1, -- 1-bit input: Clock input (S=1)
S => S -- 1-bit input: Clock select
);
-- End of BUFGMUX_inst instantiation
Verilog Instantiation Template
// BUFGMUX: Global Clock Mux Buffer
// 7 Series
// Xilinx HDL Language Template, version 2022.1
BUFGMUX #(
)
BUFGMUX_inst (
.O(O), // 1-bit output: Clock output
.I0(I0), // 1-bit input: Clock input (S=0)
.I1(I1), // 1-bit input: Clock input (S=1)
.S(S) // 1-bit input: Clock select
);
// End of BUFGMUX_inst instantiation
Related Information
- See the 7 Series FPGAs Clocking Resource User Guide (UG472).