Versal Serial I/O Hardware Debugging Flows - 2021.2 English

Vivado Design Suite User Guide: Programming and Debugging

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2021.2 English

Versal® ACAPs no longer require the generation of IBERT IP as the necessary logic required to use in-system. Serial I/O debug is now integrated into the GTY transceiver architecture. Any design that uses the GTY transceivers can be used for serial I/O hardware debugging. The Versal serial I/O hardware debugging flow has two distinct phases:

  1. Design creation. Customizing and generating a design that uses the device's GTY transceivers, typically using the Versal ACAP transceivers wizard.
  2. Serial I/O analysis. Interacting with the GTY transceivers in the design using the Vivado® Hardware Manager to debug and verify issues in your high-speed serial I/O links.
Note: Versal IBERT can use internal pattern generators such as PRBS and user data from the design. For this reason, the In-System IBERT core is not supported for Versal devices. To gain functionality similar to In-System IBERT, change the pattern to user data.
Note: Versal IBERT does not currently support rate change. Furthermore, it is not recommended to drive signals such as the PIN_EN pins on the Transceivers Wizard outside the Vivado serial I/O analyzer because it might lead to unpredictable results.

For more information, see the Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331).