On 7 series and UltraScale architectures t he Vivado Debug Hub core provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA device and the Vivado Debug cores including the following types of cores:
- Integrated Logic Analyzer (ILA)
- Virtual Input/Output (VIO)
- Integrated Bit Error Ratio Test (IBERT)
- JTAG-to-AXI
- Memory IP Important: The Vivado Debug Hub core cannot be instantiated into the design. It is inserted by Vivado during the
opt_designstage.