The Versal AXI4 Debug Hub IP and debug cores (such as AXI4-Stream ILA, AXI4-Stream VIO) offer the option to manually define the connectivity between the debug cores and the AXI4 Debug Hub. This option is not required for most designs.
To enable manual connectivity to between the AXI4 Debug Hub
and a debug core:
- Generate and instantiate an instance of the AXI4 Debug Hub IP and connect it to the Control, Interface, and Processing (CIPS) IP in the design using the PMC.
- Customize the AXI4 Debug Hub IP and set the
Number of Debug Cores to the exact
number of debug cores to be manually connected. For each debug core an
AXI4-Stream master and slave appear on the AXI4 Debug Hub IP.Note: Unconnected AXI4-Stream ports on the AXI4 Debug Hub can cause errors during
opt_design. - In the IP customization interface for the debug cores to be manually connected, select Enable AXI4-Stream Interfaces for Manual Connection to AXI Debug Hub. AXI4-Stream master and slave ports appear on the debug core.
- Connect each AXI4-Stream master and slave
port on the debug core to those on the AXI4 Debug Hub. The debug core also
includes
aclkandaresetnports, which should be connected to the same clock and reset connected to the AXI4 Debug Hub.