JTAG-to-AXI Master - 2021.2 English

Vivado Design Suite User Guide: Programming and Debugging

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2021.2 English
Note: The JTAG-to-AXI Master is not supported on Versal ACAP devices as the built-in CIPS AXI Master interfaces can be used in combination with the Debug Packet Controller (DPC) to generate AXI transactions without additional IP.

The JTAG-to-AXI Master debug feature is used to generate AXI transactions that interact with various AXI full and AXI lite slave cores in a system that is running in hardware. Xilinx recommends that you use this core to generate AXI transactions and debug/drive AXI signals internal to an FPGA at run time. This core can be used in designs without processors as well.

The IP Catalog lists this core under the Debug category. Debugging Logic Designs in Hardware of this guide has more details about the JTAG-to-AXI Master core and its usage methodology in the Vivado Design Suite. Detailed documentation on the JTAG-to-AXI IP core can be found in the JTAG to AXI Master LogiCORE IP Product Guide (PG174).