Bitstream Verify and Readback

Bitstream Verify and Readback - 2021.2 English

Vivado Design Suite User Guide: Programming and Debugging

Document ID

UG908

Release Date

2021-10-22

Version

2021.2 English

Note: The following is not applicable to Versal architectures.

Vivado^® IDE can verify and/or readback the configuration data (i.e., .bit file) downloaded into an FPGA. When using write_bitstream to generate the .bit file, use the -mask_file option to create a corresponding mask (.msk) file. Run write_bitstream -help in the Vivado IDE Tcl Console for details on bitstream generation options.

When performing a verify operation, the verify_hw_devices Tcl command reads data back from the FPGA and uses the .msk file to determine which readback data bits to skip and which ones to compare against the corresponding bits in the .bit file.

Following is an example of a bitstream verify Tcl command sequence (the .bit and .msk files were generated by a previous call to write_bitstream):

create_hw_bitstream -hw_device [current_hw_device] \
          -mask kcu105_cnt_ila_uncmpr.msk  kcu105_cnt_ila_uncmpr.bit
verify_hw_devices [current_hw_device]

You can use the Vivado Hardware Manager to verify the configuration data. Right click the device, select Verify Device as shown below.

Figure 1. Verify Device Selection

This opens up the Verify Device dialog box.

Figure 2. Verify Device Dialog

You need to enter the bit file and corresponding mask (.msk) file. Click Verify to execute the verification.

Use the readback_hw_device Tcl command with at least one of the following options to read back the FPGA configuration data:

To save readback data in ASCII format:
```
-readback_file <filename.rbd>
```
To saves readback data in binary format:
```
-bin_file <filename.bin>
```

Example: Readback FPGA configuration data in both ASCII and binary formats:

readback_hw_device [current_hw_device] \
     -readback_file  kcu105_cnt_ila_uncmpr_rb.rbd \
     -bin_file           kcu105_cnt_ila_uncmpr_rb.bin

Bitstream, and readback operations are done through the Tcl Console.
Verify and readback operations do not work for FPGAs programmed with encrypted bitstreams. Encrypted bitstreams contain commands that disable readback. Readback is re-enabled by pulsing the FPGA PROG pin, or if the FPGA/board is powered down and powered back up again.
The data readback using readback_hw_device contains configuration data only (no configuration commands are included).

For more information on the readback and mask files, see the "Verifying Readback Data" section in the UltraScale Architecture Configuration User Guide (UG570) or the 7 Series FPGAs Configuration User Guide (UG470).