QDMA Register Access (C_CPM_QDMA = 0) - 3.0 English

NVMe Target Controller LogiCORE IP Product Guide (PG329)
Document ID
PG329
Release Date
2021-10-27
Version
3.0 English
QDMA context programming register access changed to a new AXI4-Lite slave CSR interface in QDMA 4.0.

Following is the QDMA AXI4-Lite slave CSR register space table:

Table 1. QDMA AXI4-Lite Slave CSR Register Space
Register Space AXI4-Lite Slave CSR Interface Details NVMe TC
DMA Registers AXI4-Lite Slave CSR Address bit [15] is set to 1. Through this interface, only the DMA CSR register space can be accessed. This is new interface directly connected to the processor for DMA CSR register access from firmware.

Following is the QDMA AXI4-Lite slave register space table:

Table 2. QDMA AXI4-Lite Slave Register Space
Register Space AXI4-Lite Slave Interface Details NVMe TC
DMA Queue Registers AXI4-Lite Slave Address bit [29:28] is set to 2’b11. Through this interface, only the DMA Queue register space can be accessed.

This is existing interface directly connected to NVMe TC for DMA Queue register access.

Any existing context programming register access through this address space must be removed.

Following is the S_AXI_LITE and S_AXI_LITE_CSR connectivity block diagram:

Figure 1. S_AXI_LITE and S_AXI_LITE_CSR

Following is the QDMA registers table:

Table 3. QDMA Registers
Register Space Interface/Address Window Hardware Access (Intrenal to NVMETC IP) Software Access
QDMA_DMAP_SEL_INT_CIDX[2048] (0x18000)

Nvmetc

QDMA_M_AXI_LITE

0x2_0000 – 0x2_FFFF

 Yes

Yes during qdma initialization
QDMA_DMAP_SEL_H2C_DSC_PIDX[2048] (0x18004)

Nvmetc

QDMA_M_AXI_LITE

0x2_0000 – 0x2_FFFF

 Yes No
QDMA_DMAP_SEL_C2H_DSC_PIDX[2048] (0x18008)

Nvmetc

QDMA_M_AXI_LITE

0x2_0000 – 0x2_FFFF

 Yes No
QDMA_DMAP_SEL_CMPT_CIDX[2048] (0x1800C)

Nvmetc

QDMA_M_AXI_LITE

0x2_0000 – 0x2_FFFF

 Yes

Yes during qdma initialization
QDMA_REG_IND_CTXT_DATA (0x804) CSR AXI4-Lite No Yes
QDMA_REG_IND_CTXT_MASK (0x824) CSR AXI4-Lite No Yes
QDMA_REG_IND_CTXT_CMD (0x844) CSR AXI4-Lite No Yes
QDMA_REG_TRQ_SEL_FMAP (0x400) CSR AXI4-Lite No Yes
MDMA_C2H_PFCH_BYP_QID (0x1408) CSR AXI4-Lite No Yes
MDMA_C2H_PFCH_BYP_TAG (0x140c) CSR AXI4-Lite No Yes
For complete list of CSR registers, see register reference file (registration required). CSR AXI4-Lite No Yes