| dma_m_axis_c2h_tdata[C_M_AXI_DATA_WIDTH-1:0] |
O |
Data output for C2H AXI4-Stream
|
| dma_m_axis_c2h_mty[5:0] |
O |
The number of bytes that are invalid on the last beat of the
transaction |
| dma_m_axis_c2h_tvalid |
O |
Valid |
| dma_m_axis_c2h_tlast |
O |
Indicates the last cycle of the packet transfer |
| dma_m_axis_c2h_tready |
I |
Ready |
| dma_m_axis_c2h_ctrl_qid[10:0] |
O |
Queue ID |
| dma_m_axis_c2h_ctrl_len[15:0] |
O |
Length of the packet |
| dma_m_axis_c2h_ctrl_dis_cmpt |
O |
- 1'b0: The data packet has a
completion
- 1'b1: The data packet does not have a
completion
|
| dma_m_axis_c2h_ctrl_imm_data |
O |
Immediate data. This only allows the completion and no DMA on the
data payload. |
| dma_m_axis_c2h_ctrl_user_trig |
O |
User trigger. This can trigger the interrupt and the status
descriptor write if they are enabled. |
| dma_m_axis_c2h_ctrl_marker |
O |
Marker message used for making sure that the pipeline is
completely flushed |
| dma_m_axis_c2h_ctrl_port_id |
O |
Port ID |
| dma_m_axis_c2h_dpar[C_M_AXI_DATA_WIDTH/8-1:0] |
O |
Odd parity computed as bit per byte. |