Master Answer Record for the Core/Subsystem - 3.0 English

NVMe Target Controller LogiCORE IP Product Guide (PG329)

Document ID: PG329
Release Date: 2021-10-27
Version: 3.0 English

Introduction
Navigating Content by Design Process
Features
IP Facts
Overview
Control and Status Register Module
Host Submission Queue Arbitration Module
Command Validation/Decode Module
PRP Fetch Manager Module
Work Queue Manager
Work Queue Completion
Software Interface
Hardware Interface
Applications
Unsupported Features
Licensing and Ordering
License Checkers
Product Specification
Standards
Interfacing NVMe Target Controller IP with Versal ACAP CPM DMA and Bridge Mode for PCI Express configured in QDMA Mode
Introduction
Changes in NVMe Target Controller
Completion Context
Interfacing AXI Lite ports with CPM QDMA through NOC
Performance and Resource Use
Port Descriptions
NVMe Target Controller Interfaces
Interface Ports Associated with QDMA
AXI4-Stream H2C Port
AXI4-Stream C2H Port
AXI4-Stream C2H Completion Port
H2C-Streaming Bypass Input Port
H2C-Streaming Bypass Output Port Descriptions
C2H-Streaming Bypass Input Port
C2H-Streaming Cache Bypass Output Port
C2H-Streaming Simple Bypass Output Port
QDMA Master AXI Lite Port
QDMA/Host Slave AXI Lite Port
QDMA FLR Port and User Interrupt Port
Interface Ports Associated with Application
Work Queue Entry (WQE) AXI4-Stream Interface Port
Command AXI4-Stream Interface Port
Work Queue Entry (WQE) Completion AXI4-Stream Interface Port
PRG Fetch Request AXI4-Stream Interface Port
PRG Fetch Request Response AXI4-Stream Interface Port
Global Ports
Software Interface Ports
AXI4-Lite Slave Interface Ports
AXI4 Slave Interface Ports
DDR AXI4 Master Interface Ports
Register Space
AXI4-Lite Slave (sw_s_axi_lite) Memory Map
Register Map
Base Specification Registers
QDMA Register Access (C_CPM_QDMA = 0)
Designing with the Core
General Design Guidelines
Use the Example Design
Registering Signals
Recognize Timing Critical Signals
Make Only Allowed Modifications
Clocking
Resets
Design Flow Steps
Customizing and Generating the Core
Configuration Tabs
Basic Tab
Processor Interface Tab
NVMe Config Tab
User Parameters
Output Generation
NVMe I/O and Admin Commands Data Flow
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Test Bench
Verification, Compliance, and Interoperability
Upgrading
Changes from v2.0 to v3.0
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Master Answer Record for the Core/Subsystem
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debug
General Checks
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
Locating Design Files
References
Revision History
Please Read: Important Legal Notices

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