Base Specification Registers - 3.0 English

NVMe Target Controller LogiCORE IP Product Guide (PG329)
Document ID
PG329
Release Date
2021-10-27
Version
3.0 English

The following table describes the controller registers as defined by the NVMe specification and implemented by the NVMe TC IP.

Table 1. Base Specification Registers (TC SW View)
Address Offset Register Name Access Details
0x2000 +(0x40000*n) 1 Controller capabilities (CAP) RW
  • [15:0] Maximum queue entries supported.
  • [16] Continuous queues required.
  • [18:17] Arbitration mechanism supported
  • [31:24] Timeout
  • [35:32] Doorbell stride
  • [36] NVM subsystem reset supported
  • [44:37] Command sets supported.
  • [45] Boot partition support
  • [51:48] Memory page size minimum
  • [55:52] Memory page size maximum
0x2000 +(0x40000*n) + 0x8 1 Version (VS) RO
  • [7:0] Tertiary version number
  • [15:8] Minor version number.
  • [31:16] Major version number.
0x2000 +(0x40000*n) + 0xC 1 Interrupt mask set (INTMS) RO [31:0] Interrupt vector mask set
0x2000 +(0x40000*n) + 0x10 1 Interrupt mask clear (INTMC) RO [31:0] Interrupt vector mask clear
0x2000 +(0x40000*n) + 0x14 1 Controller configuration (CC) RO
  • [0] Enable
  • [6:4] I/O command set selected
  • [10:7] Memory page size
  • [13:11] Arbitration mechanism selected
  • [15:14] Shutdown notification
  • [19:16] I/O submission queue entry size
  • [23:20] I/O completion queue entry size
0x2000 +(0x40000*n) + 0x1C 1 Controller status (CSTS) RW
  • [0] Ready
  • [1] Controller fatal status
  • [3:2] Shutdown status
  • [4] NVM Subsystem Reset Occurred
  • [5] Processing paused
0x2000 +(0x40000*n) + 0x24 1 Admin queue attributes (AQA) RO
  • [11:0] Admin submission queue size
  • [27:16] Admin completion queue size
0x2000 +(0x40000*n) + 0x28 1 Admin submission queue base address (ASQ) RO [63:12] Admin submission queue base
0x2000 +(0x40000*n) + 0x30 1 Admin completion queue base address (ACQ) RO [63:12] Admin completion queue base
0x10000 + (0x40000*n) + (0x10*m) + 0xC 1, 2 Submission Queue tail doorbell (STDBL) RO [15:0] Submission Queue Tail
0x18000 + (0x40000*n) +(0x10*m) +0xC 1, 2 Completion Queue head doorbell (CQHDBL) RO [15:0] Completion Queue Head
  1. n:0. Only one function/controller is supported in this release.
  2. m: (0-64) SQ/CQs per a given function.