When the parameter C_CPM_QDMA is equal to 1, the following registers are enabled
to handle the NVMe completion entries in the NVMe Target Controller IP.
| Register (Address) | Global Address | Description |
|---|---|---|
| CMPL_CTXT_DATA_0 (0x6000) | 0x6000 + ( 256KB * N) | Completion Context data (Refer to Table 3) |
| CMPL_CTXT_DATA_1 (0x6004) | 0x6004 + ( 256KB * N) | Completion Context data (Refer to Table 3) |
| CMPL_CTXT_DATA_2 (0x6008) | 0x6008 + ( 256KB * N) | Completion Context data (Refer to Table 3) |
| CMPL_CTXT_DATA_3 (0x600C) | 0x600C + ( 256KB * N) | Completion Context data (Refer to Table 3) |
| CMPL_CTXT_CMD (0x6010) | 0x6010 + ( 256KB * N) | Table 2 |
N = Function/Controller Number and only N=0 is supported in this version of IP.
| Bit | Default | Access Type | Field | Description |
|---|---|---|---|---|
| [31:18] | 0 | N/A | Reserved | |
| [17:7] | 0 | RW | qid | Queue id. Actual qid width depends on HCQ_NUM |
| [6:5] | 0 | RW | op |
0: CLEAR 1: WRITE 2: READ 3: RESERVED |
| [4:3] | 0 | N/A | Reserved | |
| [2:1] | 0 | RO | Status |
[0]: Invalid QID [1]: Reserved
|
| [0] | 0 | RW1 | Start/Busy | Write 1 to start operation. Auto clear once done. |
| Bit | Bit Width | Field | Description |
|---|---|---|---|
| [127] | 1 | IEN | Interrupt enable |
| [126:116] | 11 | VEC | Interrupt vector |
| [115:64] | 52 | BADDR | 4K aligned base address [63:12] |
| [63] | 1 | Valid | Context Valid |
| [62:48] | 15 | Reserved | |
| [47:32] | 16 | QSIZE | Completion Queue Size |
| [31:16] | 16 | PIDX | Completion ring producer Index. This field is updated by hardware. Software must initialize it to 0 and then treat it as read-only. |
| [15:0] | 16 | CIDX | Current value of the hardware copy of the completion ring consumer index – CQDoorbell Head |