Register Map - 3.0 English

Table 1. Register Map
Address Offset	Register Name	Access	Details
0x0000	NVMe TC Interrupt status register (INTR_STS)	RO	[0] Controller enabled. This bit is set when the CC.EN bit transitions from 0 to 1. Clear CTRLR_EN_STS to clear this bit.
		RO	[1] Controller reset. This bit is set when the CC.EN bit transitions from 1 to 0. Clear CTRLR_RST_STS to clear this bit.
		RO	[2] Controller normal shutdown. This bit is set when the CC.SHN field is set to 01. Clear CTRLR_NSHN_STS to clear this bit.
		RO	[3] Controller abrupt shutdown. This bit is set when the CC.SHN field is set to 10. Clear CTRLR_ASHN_STS to clear this bit.
		RW1C	[4] QDMA WRB/CMPT Ring ID is invalidated. Check the CMPT_Q_INVLD register for more details.
		RW1C	[5] Reserved
		RW1C	[6] QDMA C2H/H2C Ring ID is invalidated. Check the QDMA_Q_INVLD register for more details
		RW1C	[7] This bit is set when the host software attempts to write an invalid doorbell value to any SQ. Check the LOG_HOST_QUEUE register to know the Host SQ ID and Function ID.
		RW1C	[8] This bit is set when the host software attempts to write an invalid doorbell value to any CQ. Check the LOG_HOST_QUEUE register to know the Host CQ ID and Function ID.
		RW1C	[9] This bit is set when the host software attempts to write the doorbell of an SQ which was not created. Check the LOG_HOST_QUEUE register to know the Host SQ ID and Function ID.
		RW1C	[10] This bit is set when the host software attempts to write the doorbell of a CQ which was not created. Check the LOG_HOST_QUEUE register to know the Host CQ ID and Function ID.
		RW1C	[11] This bit is set when fused command first part is received from the host. Check the LOG_HOST_QUEUE register to know the Host SQ ID and Function ID.
		RO	[12] Function Level Reset (PCI reset). Clear CTRLR_FLR_STS to clear this bit.
		RW1C	[13] PCIe Reset/PCIe Link Down Event.
		RW1CO	[14] PCIe Link Up EventReserved.
		RW	[15] TC Fatal errors event. Check the TC_ERR_STS register for more information.
		RW1C	[16] New Admin command available in the software queue. Check SW_Q_ATTRIBUTE [95:80] to know the number of available admin commands.
		RW1C	[17] New work request completion available for the software to read. Check WQ_CMPL_ATTRIBUTE [15:0] to know the number of work queue request completions.
		RW1C	[18] Admin Command Write Failed Error. This error occurs when the AXI Bresp error is seen by TC when pushing Admin Command on AXI Interface. Check ERR_ADMIN_CMD register for details.
		RW1C	[19] Host SQ safe deletion interrupt. Check HOST_SQ_DELETE register for details.
		RW1C	[20] PCIe Phy Ready event.
0x0004	QDMA Reset Control Status register (QDMA_CS)	RW	[0] – qdma_usr_reset_n Reset the QDMA logic through the soft_reset_n port. This port needs to be held in reset for a minimum of 100 clock cycles (axi_aclk cycles) 0: reset 1: clear reset
		RO	[8] - pcie_link_up
		RO	[9] – pcie_phy_ready
		RW1C	[16] – axi_resetn, core reset interrupt status register, non-maskable
0x0008	NVMe TC Interrupt enable register (INTR_EN)	RW	Bitwise interrupt enable bit for INTR_STS
0x000C	NVMe TC Configuration (TC_CFG)	RW	[15:0] Maximum Host I/O SQ/CQ Depth. Applicable for all functions. Default value is C_CAP_MAX_HOST_Q_DEPTH [18:16] Arbitration Burst. Applicable for all functions. Default value is C_ARB_BURST [23:19] Reserved. [31:24] Timeout. Applicable for all Functions. Default value is C_CAP_TIMEOUT
0x0010	NVMe TC IP Control Register (TC_CTRL)	RW	[0] Setting this bit halts the NVMe TC [1] Setting this bit to 1 stops fetching of the command from all host SQs, including ASQ [2] Setting this bit to 1 stops the Work Queue Arbitration between software and hardware and processing of WQEs [3] Setting this bit to 1 initializes the UID index FIFO. [7:3] Reserved [15:8] Maximum outstanding command fetch requests at QDMA. Value zero means unlimited [16] NVMe registers write access enable, except AQA, ASQ, ACQ registers, across all functions. [17] NVMe registers write access enable, including AQA, ASQ, ACQ registers, across all functions. [23:18] Reserved
0x0014	Function Level Interrupt Clear (FUNC_INTR_CLR)	RW	[7:0] Function ID [15:8] Reserved [19:16] Interrupt Clear Opcode 4’h0 - FLR Interrupt clear [31:20] Reserved
0x0018	Host SQ/CQ ID logging (LOG_HOST_QUEUE)	RO	[15:0] Host Submission Queue ID is logged here when INTR_STS [7] or INTR_STS [9] [31:16] Host Submission Controller ID is logged here when INTR_STS [7] or INTR_STS [9] bits are set. [47:32] Host Completion Queue ID is logged here when INTR_STS [8] or INTR_STS [10] [63:48] Host Completion Controller ID is logged here when INTR_STS [8] or INTR_STS [10] bits are set.
0x0020	NVMe TC IP Status Register (TC_STS)	RO	[0] NVMe TC IP functionality halted. This bit is set in response to TC_CTRL [0] bit set [1] NVMe TC IP stopped HSQ arbitration and fetching. This bit is set in response to TC_CTRL [1] bit set [2] NVMe TC IP stopped WQE arbitration and processing. This bit is set in response to TC_CTRL [2] bit set. [3] UID index FIFO Initialization is done. This bit is set in response to TC_CTRL [3] bit set. [31:3] Reserved
0x0024	Work Queue Completion Attributes (WQ_CMPL_ATTRIBUTE)	RO	[15:0] Number of available completions [31:16] Reserved
0x0028	Legacy Interrupt Enable (LEGACY_INTR_EN)	RW	[0] Enable Legacy Interrupt
0x002C	Global Prefetch Bypass Tag (GLOBAL_PFCH_BYP_TAG)	RW	[10:0] QDMA_C2H_PFCH_BYP_QID [15:11] Reserved [22:16] QDMA_C2H_PFCH_BYP_TAG [23] Reserved [24] tag_valid [31:25] Reserved
0x0030	Software Queue Attribute (SW_Q_ATTRIBUTE)	RW	[63:0] Software Queue Base Address
		RW	[79:64] Software Queue Size. Zero based value
		RO	[95:80] Number of available admin commands
		RO	[111: 96] Software Admin Queue Write/tail Pointer
		RW	[127: 112] Softwaare Admin Queue Read/head pointer
0x0040	QDMA_Q_INVLD	RO	[10:0] QDMA QID which is deleted/aborted [13:11] Port ID [14] Error [15] Queue Invalidated [16] Queue Enabled [17] Bypass Mode [18] 0 – H2C, 1 – C2H [31:21] Credits
0x0044	CMPT_Q_INVLD	RO	[10:0] axis_c2h_status_qid [16] axis_c2h_status_last [18] axis_c2h_status_cmp
0x0048	ERR_ADMIN_CMD	RO	[15:0] CMDID of the errored Admin Command [23:16] Function ID
0x004C	HOST_SQ_DELETE	RO	[15:0] HSQ ID to be deleted [23:16] Function ID
0x0050	DATA_BUF_BA_0	RW	Local Data Buffer LSB 32-bit address
0x0054	DATA_BUF_BA_1	RW	Local Data Buffer MSB 32-bit address
0x0058	PRP_BUF_BA_0	RW	PRP Buffer LSB 32-bit Address
0x005C	PRP_BUF_BA_1	RW	PRP Buffer LSB 32-bit Address
0x0060	Debug Control (DBG_CTRL)	RW	[1] dbg_cmd_err_inj_en [2] dbg_cqe_sts_zero_en [8] dbg_sw_wqcmpl_fifo_overwrite [9] dbg_cmd_val_check_dis [10] dbg_parity_type [11] dbg_cmd_pool_rd_en [19:16] dbg_reg_indx [31:20] dbg_wqe_fifo_addr
0x0064	NVMe TC Fatal Errors (TC_ERR_STS)	RO	[0] c2h_wqe_fifo_overrun [1] h2c_wqe_fifo_overrun [2] hw_unexpected_sqid [3] sw_unexpected_sqid [4] h2c_wqcmpl_fifo_overrun [5] h2c_zero_len_dma [7:6] Reserved [8] c2h_axi_req_fifo_overrun [9] c2h_axi_rsp_fifo_overrun [10] c2h_zero_len_dma [11] Reserved [12] Unexpected CMPT [13] Unsupported WQE opcode [15:14] Reserved [16] SW Q overrun [17] SW Credits Underrun [18] SW wq cmpl read on empty by SW [19] h2c stream context fifo underrun [20] axi_wr_error [21] axi_rd_error [22] axi wr req fifo overrun [23] axi rd req fifo overrun [24] axi wr req fifo underrun [25] axi rd req fifo underrun [27:26] Reserved [28] sw_q_hdbl_invld [29] sw_q_hdbl_out_of_range [63:30] Reserved
0x0070	Debug Window Counter (DBG_WIN_CNT)	RW	[0] Window Counter Enable [1] Clear all debug counters [31:4] Window Counter Time
0x0074	Module Reset Enable (MRE)	RW1C	[0] NVMe TC Module Reset Enable. This bit is auto set on PCIe link down event
0x0078	Module Reset Done (MRD)	RO	[0] NVMe TC module reset done
0x0100	Each Controller Enable status register (CTRLR_EN_STS)	RW1C	[255:0] Each bit position when set represents that the corresponding controller is enabled.
0x0120	Each Controller Reset status register (CTRLR_RST_STS)	RW1C	[255:0] Each bit position when set represents that the corresponding controller is in reset.
0x0140	Each Controller Normal Shutdown status register (CTRLR_NSHN_STS)	RW1C	[255:0] Each bit position when set represents that the corresponding controller is in normal shutdown
0x0160	Each Controller Abrupt Shutdown status register (CTRLR_ASHN_STS)	RW1C	[255:0] Each bit position when set represents that the corresponding controller is in abrupt shutdown
0x01A0	Each Controller FLR Status (CTRLR_FLR_STS)	RO	[255:0] Each bit position when set represents that the corresponding controller received FLR. Program FUNC_INTR_C2R to clear this bit
0x01D0	TC_CFG_QUEUE_NUM	RW	[10:0] Host SQs per functions, including ASQ. Default/Maximum value is C_MAX_HSQ_PER_FUNC [26:16] Host CQs per functions, ncluding ACQ. Default/maximum value is C_MAX_HSQ_PER_FUNC
0x01D4	TC_CFG_MDTS	RW	[7:0] Maximum data transfer size (MDTS).
0x01D8	TC_CFG_SW_WQE_CR	RW	[7:0] Software credits for work queue entries. Default/Maximum value is 32.
0x01DC	TC_CFG_NUM_FUNC	RW	[7:0] Number of functions/controllers. Default/Maximum value is C_MAX_FUNC.
0x01E0	Reserved	RO	Reserved
0x01E4	TC_CFG_SGL_SUPPORT	RW	[0] SGL Support Note: SGL is not supported in this release.
0x01E8	TC_CFG_NSZE_LO	RW	[31:0] Lower 32 bits of Namespace size. This is used in identify response of TC standalone scenario.
0x01EC	TC_CFG_NSZE_UP	RW	[31:0]: Upper 32 bits of Namespace size. This is used in identify response of TC standalone scenario.
0x0200	DBG_SGL_PRP	RO	[127:0] PRP debug and status information
0x0210	DBG_CMD_FETCH	RO	[3:0] cmd_fetch_cs [5:4] hsq_arb_cs [6] sw_q_full_early [7] h2c_byp_in_vld [11:8] cmd_val_cs [12] Internal Arbitration FIFO full [13] Internal Arbitration FIFO empty [14] No free UID indexes
0x0214	DBG_CMD_VAL	RO	Reserved
0x0218	DBG_PCIE_LINK_STS	RO	[0] pcie_link_up [1] pcie_phy_ready
0x021C	DBG_CMD_CNT	RO	[15:0] Number of admin commands pushed to the software queue. [31:16] Number of I/O commands pushed to the hardware IP module.
0x0220	DBG_WQE_FIFO	RO	[0] sgl_prp_wqe_fifo_empty [1] sgl_prp_wqe_fifo_afull [2] sgl_prp_wqe_fifo_full [3] Reserved [4] sw_c2h_wqe_fifo_empty [5] sw_c2h_wqe_fifo_afull [6] sw_c2h_wqe_fifo_full [7] Reserved [8] hw_c2h_wqe_fifo_empty [9] hw_c2h_wqe_fifo_afull [10] hw_c2h_wqe_fifo_full [11] Reserved [12] hw_h2c_wqe_fifo_empty [13] hw_h2c_wqe_fifo_afull [14] hw_h2c_wqe_fifo_full [15] Reserved [16] sw_cmpt_wqe_fifo_empty [17] sw_cmpt_wqe_fifo_afull [18] sw_cmpt_wqe_fifo_full [19] Reserved [20] sw_cmpt_wqe_fifo_empty [21] sw_cmpt_wqe_fifo_afull [22] sw_cmpt_wqe_fifo_full [23] Reserved [24] hw_cmpt_wqe_fifo_empty [25] hw_cmpt_wqe_fifo_afull [26] hw_cmpt_wqe_fifo_full [31:27] Reserved
0x0224	DBG_WQE_H2C	RO	[3:0] wqe_mgr_cs [4] h2c_data_wr_req_fifo_full [5] h2c_cmpl_fifo_full [6] h2c_data_wr_req_fifo_empty [7] h2c_cmpl_fifo_empty [15] h2c_data_buf_not_avail
0x0228	DBG_WQE_C2H	RO	[3:0] data_rd_cs [7:4] post_wqe_cs [16] axi_rsp_empty [17] axi_rsp_afull [18] axi_rsp_full [19] post_wqe_empty [20] post_wqe_afull [21] post_wqe_full
0x022C	DBG_WQE_CMPT	RO	[3:0] cmpt_wqe_cs
0x0230	DBG_CMPT_IN_CNT	RO	[15:0] Number of software command completions received by the TC. [31:16] Number of I/O command completions received by the TC.
0x0234	DBG_CMPT_OUT_CNT	RO	[15:0] Number of software command completions pushed to the QDMA. [31:16] Number of I/O command completions pushed to the QDMA.
0x0238	DBG_CMPT_CMPL_CNT	RO	[15:0] Number of software command completion responses to software. [31:16] Number of I/O command completion responses to the hardware IP.
0x023C	DBG_SW_DMA_CNT	RO	[15:0] Number of software C2H DMA work request counts. [31:16] Number of PRP DMA work request counts.
0x0240	DBG_HW_DMA_CNT	RO	[15:0] Number of hardware IP C2H DMA work request count. [31:16] Number of hardware IP H2C DMA work request count.
0x0244	DBG_DMA_POP_CNT	RO	[15:0] Number of C2H DMA work request pops. [31:16] Number of H2C DMA work request pops.
0x0248	DBG_DMA_PUSH_CNT	RO	[15:0] Number of C2H DMA pushed to QDMA. [31:16] Number of H2C DMA pushed to QDMA.
0x024C	DBG_DMA_RSP_CNT	RO	[15:0] Number of C2H DMA completed. [31:16] Number of H2C DMA completed.
0x0260 – 0x029C	DBG_TC_TOP	RO	[511:0] NVMe TC IP debug information.
0x10000 + (0x40000n) + (0x10m)^{1, 2}	Host SQ Attributes (HSQ_ATTRIBUTE)	RW	[10:0] Host Submission Queue ID to QDMA QP ID Mapping [15:112] Reserved [23:16] Reserved [24] Host Submission Queue Enable/Disable [25] Host Submission Queue Arbitration disable [26] Reserved [27] SQ deletion pending bit [31:28] Reserved [47:32] Outstanding Commands for this SQ [63:48] Last PIDX value updated to QDMA QID [79:64] Host Submission Queue Size³, Zero based value [95:80] Host CQ ID mapped to this SQ
0x10000 + (0x40000n) + (0x10m)^{1, 2}	Host SQ Attributes (HSQ_ATTRIBUTE)	RO	[111:96] Host Submission Queue Tail pointer [127:112] Host Submission Queue Head pointer
0x18000 + (0x40000n) +(0x10m)^{1, 2}	Host CQ Attributes (HCQ_ATTRIBUTE)	RW	[10:0] Host Completion Queue ID to QDMA QP ID Mapping [15:112] Reserved [23:16] Reserved [24] Host Completion Queue Enable/Disable [25] Host Completion Queue Interrupt Enable [63:26] Reserved [79: 64] Host Completion queue size³, Zero based value. [80] Host Completion Queue Phase bit.
0x18000 + (0x40000n) +(0x10m)^{1, 2}	Host CQ Attributes (HCQ_ATTRIBUTE)	RO	[111: 96] Host Completion Queue Tail Pointer [127: 112] Host Completion Queue Head Pointer
n: 0. Only one function/controller is supported in this release. m: (0-64) SQ/CQs per a given function. Size for admin SQ/CQ is written as part of the AQA register write by the host.