The NVMe Target Controller IP provides the following features on the host side and application/user logic side interface.
Features on the host side include:
- Configurable number of host side SQ/CQs per controller (maximum of 64)
- Configurable depth of SQ/CQs
- Support for the PRP
- Command parsing for errors
- MSI-x interrupt generation handling
Features on the application side include:
- Offloads the application/user logic from complete QDMA programing
- Admin queues are mapped to software while the I/O queues are mapped to the hardware user logic interface
- Memory-mapped AXI4 interface for software to post “instructions” to NVMe TC
- AXI4-Stream interface for hardware application/module to post “instruction” to NVMe TC