QDMA FLR Port and User Interrupt Port - 3.0 English

NVMe Target Controller LogiCORE IP Product Guide (PG329)

Document ID: PG329
Release Date: 2021-10-27
Version: 3.0 English

Note: FLR is not supported in this release.

Table 1. QDMA FLR Port Descriptions
Port Name	I/O	Description
i_flr_set	I	Set Asserted for one cycle indicating that the FLR status of the function indicated on `i_flr_fid[[7:0]` is active.
i_flr_clr	I	Clear Asserted for one cycle indicating that the FLR status of the function indicated on `i_flr_fid[7:0]` is completed.
i_flr_fid[7:0]	I	Function: The function number of the FLR status change.
o_flr_done_fid[7:0]	O	Done Function: The function for which the FLR is completed by user logic.
o_flr_done_vld	O	Done Valid Assert for one cycle to signal that FLR for the function on `o_flr_done_fid[7:0]` is completed.

Table 2. User Interrupt Port Descriptions
Port Name	I/O	Description
o_usr_irq_out_vld	O	Valid. An assertion indicates that an interrupt associated with the vector, function, and pending fields on the bus must be generated to PCIe. Once asserted, `usr_irq_in_vld` must remain high until the DMA asserts `usr_irq_out_ack`.
o_usr_irq_out_vec[4:0]	O	Vector. The MSIX Vector to sent.
o_usr_irq_out_fnc[7:0]	O	Function. The function of the vector to be sent.
i_usr_irq_in_ack	I	Interrupt Acknowledge. An assertion of the acknowledged bit indicates that the interrupt is transmitted on the link. The user logic must wait for this pulse before signaling to another interrupt condition.
i_usr_irq_in_fail	I	Interrupt Fail An assertion of fail indicates that the interrupt request was aborted before the transmission on the link was completed.