For the independent clock FIFO, there are delays in the assertion/deassertion of the full and empty flags due to cross clock domain logic. These delays can cause unexpected FIFO behavior like full and empty asserting at the same time. To avoid this, the following A and B equations must be true.
A) Time it takes to update full flag due to read operation < time it takes to empty a full FIFO
B) Time it takes to update empty flag due to write operation < time it takes to fill an empty FIFO
For example, assume the following configurations:
- Independent clock (non built-in), standard FIFO
- write clock frequency = 3 MHz, wr_clk_period = 333 ns
- read clock frequency = 148 MHz, rd_clk_period = 6.75 ns
- write depth = read depth = 20
- actual_wr_depth = actual_rd_depth = 19 (as specified in Actual FIFO Depth)
- N = number of synchronization stages. In this example, N = 2
Apply Equation A:
Time it takes to update full flag due to read operation < time it takes to empty a full FIFO = 1*rd_clk_period + (3 + N)*wr_clk_period < actual_rd_depth*rd_clk_period
1*6.75 + 5*333 < 19*6.75
1671.75 ns < 128.5 ns --> Equation VIOLATED!
Conclusion: Violation of this equation proves that for this design, when a full FIFO is read from continuously, the empty flag asserts before the full flag deasserts due to the read operations that occurred.
Apply Equation B:
Time it takes to update empty flag due to write operation < time it takes to fill an empty FIFO
1*wr_clk_period + (3 + N)*rd_clk_period < actual_wr_depth*wr_clk_period
1*333 + 5*6.75 < 19*333
366.75 ns < 6327 ns --> Equation MET!
Conclusion: Because this equation is met for this design, an empty FIFO that is written into continuously has its empty flag deassert before the full flag is asserted.