Native FIFO Interface Signals - 1.0 English

Embedded FIFO Generator LogiCORE IP Product Guide (PG327)

Document ID
PG327
Release Date
2023-05-10
Version
1.0 English

The following sections define the FIFO interface signals. The following figure illustrates these signals (both standard and optional ports) for a FIFO core that supports independent write and read clocks.

Figure 1. FIFO with Independent Clocks: Interface Signals
Note: Optional ports are represented in italics.

Interface Signals: FIFOs With Independent Clocks

The rst signal, as defined in the following table, causes a reset of the entire core logic (both write and read clock domains. The initial hardware reset should be generated by the user.
Table 1. Reset and Sleep Signals for FIFOs with Independent Clocks
Name Direction Description
rst Input Reset: A synchronous reset signal that initializes all internal pointers and output registers.
sleep Input

Dynamic power gating. If sleep is active, the FIFO is in power saving mode.

Only available for UltraRAM FIFOs.

The following table defines the write interface signals for FIFOs with independent clocks. The write interface signals are divided into required and optional signals and all signals are synchronous to the write clock (wr_clk).
Table 2. Write Interface Signals for FIFOs with Independent Clocks
Name Direction Description
Required
wr_clk Input Write Clock: All signals on the write domain are synchronous to this clock.
din[n:0] Input Data Input: The input data bus used when writing the FIFO.
wr_en Input Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO.
full Output Full Flag: When asserted, this signal indicates that the FIFO is full. Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive to the contents of the FIFO.
Optional
almost_full Output Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.
prog_full Output Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold. It is deasserted when the number of words in the FIFO is less than the negate threshold.
wr_data_count [d:0] Output Write Data Count: This bus indicates the number of words written into the FIFO. The count is guaranteed to never under-report the number of words in the FIFO, to ensure you never overflow the FIFO. The exception to this behavior is when a write operation occurs at the rising edge of wr_clk/clk, that write operation will only be reflected on wr_data_count at the second rising clock edge. If D is less than log2(FIFO depth)-1, the bus is truncated by removing the least-significant bits.
wr_ack Output Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle succeeded.
overflow Output Overflow: This signal indicates that a write request (wr_en) during the prior clock cycle was rejected, because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO.
injectsbiterr Input Injects a single bit error if the ECC feature is used on block RAMs or UltraRAM FIFO macros.
injectdbiterr Input Injects a double bit error if the ECC feature is used on block RAMs or UltraRAM FIFO macros.
wr_rst_busy Output When asserted, this signal indicates that the write domain is in reset state.
The following table defines the read interface signals of a FIFO with independent clocks. Read interface signals are divided into required signals and optional signals, and all signals are synchronous to the read clock (rd_clk).
Table 3. Read Interface Signals for FIFOs with Independent Clocks
Name Direction Description
Required
rd_clk Input Read Clock: All signals on the read domain are synchronous to this clock.
dout[m:0] Output Data Output: The output data bus is driven when reading the FIFO.
rd_en Input Read Enable: If the FIFO is not empty, asserting this signal causes data to be read from the FIFO (output on dout).
empty Output Empty Flag: When asserted, this signal indicates that the FIFO is empty. Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO.
Optional
almost_empty Output Almost Empty Flag: When asserted, this signal indicates that the FIFO is almost empty and one word remains in the FIFO.
prog_empty Output Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable threshold. It is de-asserted when the number of words in the FIFO exceeds the programmable threshold.
rd_data_count [c:0] Output Read Data Count: This bus indicates the number of words available for reading in the FIFO. The count is guaranteed to never over-report the number of words available for reading, to ensure that you do not underflow the FIFO. The exception to this behavior is when the read operation occurs at the rising edge of rd_clk/clk, that read operation is only reflected on rd_data_count at the second rising clock edge. If C is less than log2(FIFO depth)-1, the bus is truncated by removing the least-significant bits.
data_valid Output Data Valid: This signal indicates that valid data is available on the output bus (dout).
underflow Output Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected because the FIFO is empty. Underflowing the FIFO is not destructive to the FIFO.
sbiterr Output Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error on block RAM or UltraRAM FIFO macro.
dbiterr Output Double Bit Error: Indicates that the ECC decoder detected a double-bit error on block RAM or UltraRAM FIFO macro and data in the FIFO core is corrupted.
rd_rst_busy Output When asserted, this signal indicates that the read domain is in reset state.

Interface Signals: FIFOs with Common Clock

The following table defines the interface signals of a FIFO with a common write and read clock and is divided into standard and optional interface signals. All signals are synchronous to the common clock (clk).
Table 4. Interface Signals for FIFOs with a Common Clock
Name Direction Description
Required
rst Input Reset: A synchronous reset that initializes all internal pointers and output registers.
clk Input Clock: All signals on the write and read domains are synchronous to this clock.
din[n:0] Input Data Input: The input data bus used when writing the FIFO.
wr_en Input Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO.
full Output Full Flag: When asserted, this signal indicates that the FIFO is full. Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive to the contents of the FIFO.
dout[m:0] Output Data Output: The output data bus driven when reading the FIFO.
rd_en Input Read Enable: If the FIFO is not empty, asserting this signal causes data to be read from the FIFO (output on dout).
empty Output Empty Flag: When asserted, this signal indicates that the FIFO is empty. Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO.
Optional
wr_data_count [c:0] Output Data Count: This bus indicates the number of words stored in the FIFO. If C is less than log2(FIFO depth)-1, the bus is truncated by removing the least-significant bits.
almost_full Output Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.
prog_full Output Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold. It is deasserted when the number of words in the FIFO is less than the negate threshold.
wr_ack Output Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle succeeded.
overflow Output Overflow: This signal indicates that a write request (wr_en) during the prior clock cycle was rejected, because the FIFO is full. Overflowing the FIFO is not destructive to the FIFO.
almost_empty Output Almost Empty Flag: When asserted, this signal indicates that the FIFO is almost empty and one word remains in the FIFO.
prog_empty Output Programmable Empty: This signal is asserted after the number of words in the FIFO is less than or equal to the programmable threshold. It is de-asserted when the number of words in the FIFO exceeds the programmable threshold.
data_valid Output Data Valid: This signal indicates that valid data is available on the output bus (dout).
underflow Output Underflow: Indicates that read request (rd_en) during the previous clock cycle was rejected because the FIFO is empty. Underflowing the FIFO is not destructive to the FIFO.
sbiterr Output Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.
dbiterr Output Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.
injectsbiterr Input Injects a single bit error if the ECC feature is used. For detailed information.
injectdbiterr Input Injects a double bit error if the ECC feature is used. For detailed information.
sleep Input Dynamic shutdown power saving. If sleep is active, the FIFO is in power saving mode.
wr_rst_busy Output When asserted, this signal indicates that the write domain is in reset state.
rd_rst_busy Output When asserted, this signal indicates that the read domain is in reset state.