The Embedded FIFO Generator core is a fully verified first-in first-out memory queue for use in any application requiring ordered storage and retrieval, enabling high-performance and area-optimized designs. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while using minimum resources.
This core supports Native interface FIFOs, AXI Memory Mapped interface FIFOs and AXI4-Stream interface FIFOs. AXI Memory Mapped and AXI4-Stream interface FIFOs are derived from the Native interface FIFO. Two AXI Memory Mapped interface styles are available: AXI4 and AXI4-Lite.
This core can be customized using the AMD Vivado™
IP customizers in the IP catalog as a complete solution with
control logic already implemented, including management of the read and write pointers
and the generation of status flags.
Note: The Memory Mapped interface FIFO and AXI4-Stream interface FIFO are referred to as AXI FIFO throughout this
document.