Common Clock and Standard Read Mode Implementations - 1.0 English - PG327

Embedded FIFO Generator LogiCORE IP Product Guide (PG327)
Document ID
PG327
Release Date
2023-05-16
Version
1.0 English

The following table defines the write port flags update latency due to a write operation.

Table 1. Write Port Flags Update Latency Due to Write Operation
Signals Latency (clk)
full 0
almost_full 0
prog_full 1
wr_ack 0
overflow 0

The following table defines the read port flags update latency due to a read operation.

Table 2. Read Port Flags Update Latency Due to Read Operation
Signals Latency (clk)
empty 0
almost_empty 0
prog_empty 1
data_valid 0
underflow 0
wr_data_count 1

The following table defines the write port flags update latency due to a read operation.

Table 3. Write Port Flags Update Latency Due to Read Operation
Signals Latency (clk)
full 0
almost_full 0
prog_full 1
wr_ack 1 N/A
overflow 1 N/A
  1. Write handshaking signals are only impacted by a write operation.

The following table defines the read port flags update latency due to a write operation.

Table 4. Read Port Flags Update Latency Due to Write Operation
Signals Latency (clk)
empty 0
almost_empty 0
prog_empty 0
valid 1 N/A
underflow 1 N/A
data_count 0
  1. Read handshaking signals are only impacted by a read operation.