Independent Clock and FWFT Read Mode Implementations - 1.0 English

Embedded FIFO Generator LogiCORE IP Product Guide (PG327)
Document ID
PG327
Release Date
2023-05-16
Version
1.0 English

The following table defines the write port flags update latency due to a write operation.

Table 1. Write Port Flags Update Latency Due to a Write Operation
Signals Latency (wr_clk)
full 0
almost_full 0
prog_full 1
wr_ack 0
overflow 0
wr_data_count 1

The following table defines the read port flags update latency due to a read operation.

Table 2. Read Port Flags Update Latency Due to a Read Operation
Signals Latency (rd_clk)
empty 0
almost_empty 0
prog_empty 1
data_valid 0
underflow 0
rd_data_count 1

The following table defines the write port flags update latency due to a read operation. N is the number of synchronization stages. In this example, N is 2.

Table 3. Write Port Flags Update Latency Due to a Read Operation
Signals Latency
full 1 rd_clk + (N + 2) wr_clk (+1 wr_clk) 1
almost_full 1 rd_clk + (N + 2) wr_clk (+1 wr_clk) 1
prog_full 1 rd_clk + (N + 3) wr_clk (+1 wr_clk) 1
wr_ack 2 N/A
overflow 2 N/A
wr_data_count 1 rd_clk + (N + 2) wr_clk (+1 wr_clk) 1
  1. The crossing clock domain logic in independent clock FIFOs introduces a 1 wr_clk uncertainty to the latency calculation.
  2. Write handshaking signals are only impacted by a write operation.

The following table defines the read port flags update latency due to a write operation. N is the number of synchronization stages. In this example, N is 2.

Table 4. Independent Clock FWFT
Signals No Register
  Latency(clk)
empty 1 wr_clk + (N + 4) rd_clk (+1 rd_clk) 1
almost_empty 1 wr_clk + (N + 4) rd_clk (+1 rd_clk) 1
prog_empty 1 wr_clk + (N + 3) rd_clk (+1 rd_clk) 1
data_valid 2 N/A
underflow 2 N/A
rd_data_count 1 wr_clk + (N + 2) rd_clk (+1 rd_clk) 1 + [N rd_clk (+1 rd_clk)] 3
  1. The crossing clock domain logic in independent clock FIFOs introduces a 1 rd_clk uncertainty to the latency calculation
  2. Read handshaking signals are only impacted by a read operation.
  3. This latency is the worst-case latency. The addition of the [2 rd_clk (+1 rd_clk)] latency depends on the status of the empty and almost_empty flags.