data_count
tracks the number of words in the FIFO. You can specify the width of
the data count bus with a maximum width of log2 (FIFO depth). If the width specified is
smaller than the maximum allowable width, the bus is truncated by removing the lower
bits. These signals are optional outputs of the FIFO Generator core, and are enabled
through the Vivado IDE. The following table identifies data count support for each FIFO
implementation. For information about the latency behavior of data count flags, see
Latency.
FIFO Implementation | Data Count Support | |
---|---|---|
Independent Clocks | Block RAM | ü |
Distributed RAM | ✓ | |
Built-in | ||
Common Clock | Block RAM | ✓ |
Distributed RAM | ✓ | |
Shift Register | ✓ | |
Built-in |
Data Count (Common Clock FIFO Only)
Data Count output (data_count
) accurately reports the number of
words available in a Common Clock FIFO. You can specify the width of the data count
bus with a maximum width of log2(depth). If the width specified is smaller than the
maximum allowable width, the bus is truncated with the lower bits removed.
clk
, the data count port is updated at the same rising
edge of clk
.Read Data Count
Read data count (rd_data_count
) pessimistically reports the number
of words available for reading. The count is guaranteed to never over-report the
number of words available in the FIFO (although it may temporarily under-report the
number of words available) to ensure that the user design never underflows the FIFO.
You can specify the width of the read data count bus with a maximum width of log2
(read depth). If the width specified is smaller than the maximum allowable width,
the bus is truncated with the lower bits removed.
rd_clk
/clk
, that read is reflected on the
rd_data_count
signal following the next rising clock edge.
A write operation on the wr_clk
/clk
clock
domain may take a number of clock cycles before being reflected in the
rd_data_count
.Write Data Count
Write data count (wr_data_count
) pessimistically reports the number
of words written into the FIFO. The count is guaranteed to never under-report the
number of words in the FIFO (although it may temporarily over-report the number of
words present) to ensure that you never overflow the FIFO. You can specify the width
of the write data count bus with a maximum width of log2 (write depth). If the width
specified is smaller than the maximum allowable width, the bus is truncated with the
lower bits removed.
wr_clk
/clk
, that write will be reflected on
the wr_data_count
signal following the next rising clock edge.
A read operation, which occurs on the
rd_clk
/clk
clock domain, may take a number
of clock cycles before being reflected in the
wr_data_count
.First-Word Fall-Through Data Count
- Approximate Data Count
- More Accurate Data Count (Use Extra Logic)
Approximate Data Count behavior is
the default option in the Vivado IDE for independent clock block RAM and distributed
RAM FIFOs. This feature is not available for common clock FIFOs. The width of the
wr_data_count
and rd_data_count
is identical
to the non first-word-fall-through configurations (log2 (write depth) and log2 (read
depth), respectively) but the data counts reported is an approximation because the
actual full depth of the FIFO is not supported.
Using this option, you can
use specific bits in wr_data_count
and
rd_data_count
to approximately indicate the status of the FIFO,
for example, half full, quarter full, and so forth.
For example, for a FIFO
with a depth of 16, symmetric read and write port widths, and the
first-word-fall-through option selected, the actual FIFO depth increases from
15 to 17. When using approximate data count, the width of
wr_data_count
and rd_data_count
is 4 bits,
with a maximum of 15. For this option, you can use the assertion of the MSB bit of
the data count to indicate that the FIFO is approximately half full.
This feature is enabled when Use
Extra Logic for More Accurate Data Counts is selected in the Vivado IDE. In this
configuration, the width of wr_data_count
,
rd_data_count
, and data_count
is log2(write
depth)+1, log2(read depth)+1, and log2(depth)+1, respectively to accommodate the
increase in depth in the first-word-fall-through case and to ensure accurate data
count is provided.
wr_data_count
, rd_data_count
, and
data_count
to indicate the status of the FIFO, for example,
approximately half full, quarter full, and so forth.For example, for an
independent FIFO with a depth of 16, symmetric read and write port widths, and the
first-word-fall-through option selected, the actual FIFO depth increases from
15 to 17. When using accurate data count, the width of the
wr_data_count
and rd_data_count
is 5 bits,
with a maximum of 31. For this option, you must use the assertion of both the MSB
and MSB-1 bit of the data count to indicate that the FIFO is at least half
full.
Data Count Behavior
For FWFT implementations using More Accurate Data Counts (Use Extra Logic),
data_count
is guaranteed to be accurate when words are present
in the FIFO, with the exception of when its near empty or almost empty or when
initial writes occur on an empty FIFO. In these scenarios,
data_count
may be incorrect on up to two words.
The following table defines the value of data_count
when FIFO is
empty.
From the point-of-view of the write interface, data_count
is always
accurate, reporting the first word immediately once its written to the FIFO.
However, from the point-of-view of the read interface, the
data_count
output may over-report by up to two words until
almost_empty
and empty
have both deasserted.
This is due to the latency of empty
deassertion in the
first-word-fall-through FIFO. This latency allows data_count
to
reflect written words which may not yet be available for reading.
almost_empty
deasserts. Before
almost_empty
deasserts, the data_count
signal
may exhibit the following behaviors: - From the read-interface perspective,
data_count
may over-report up to two words.
Write Data Count Behavior
Even for FWFT implementations using More Accurate Data Counts (Use Extra Logic),
wr_data_count
will still pessimistically report the number of
words written into the FIFO. However, the addition of this feature will cause
wr_data_count
to further over-report up to two read words (and
1 to 16 write words, depending on read and write port aspect ratio) when the FIFO is
at or near empty or almost empty.
The following table defines the value of wr_data_count
when the FIFO
is empty.
wr_data_count
starts to transition out
of over-reporting two extra read words at the deassertion of empty
. This transition completes several clock cycles
after almost_empty
deasserts. Note that prior to
the transition period, wr_data_count
will always
over-report by at least two read words. During the transition period, the wr_data_count
signal may exhibit the following strange
behaviors: -
wr_data_count
may decrement although no read operation has occurred. -
wr_data_count
may not increment as expected due to a write operation.
wr_data_count
and data_count
value is set to 0.Write Depth to Read Depth Ratio | Approximate wr_data_count | More Accurate wr_data_count | More Accurate data_count |
---|---|---|---|
1:1 | 0 | 2 | 2 1 |
1:2 | 0 | 1 1 | N/A |
1:4 | 0 | 0 | N/A |
1:8 | 0 | 0 | N/A |
2:1 | 0 | 4 | N/A |
4:1 | 0 | 8 | N/A |
8:1 | 0 | 16 | N/A |
|
The rd_data_count value at empty (when no write is performed) is 0 with or without Use Extra Logic for all write depth to read depth ratios.
Example Operation
The following figure shows write and read data counts. When wr_en
is
asserted and full
is deasserted, wr_data_count
increments. Similarly, when rd_en
is asserted and
empty
is deasserted, rd_data_count
decrements.
In the first part of the following figure, a successful write operation occurs on the
third rising clock edge, and is not reflected on wr_data_count
until the next full clock cycle is complete. Similarly,
rd_data_count
transitions one full clock cycle after a
successful read operation.