Built-in ECC is supported for FIFOs configured with block RAM and UltraRAM
FIFOs. When ECC is enabled, the block RAM and UltraRAM FIFO primitive used to create the
FIFO is configured in the full ECC mode (both encoder and decoder enabled), providing
two additional outputs to the Embedded FIFO Generator core:
sbiterr and dbiterr.
These outputs indicate three possible read results: no error, single error corrected,
and double error detected. In the full ECC mode, the read operation does not correct the
single error in the memory array, it only presents corrected data on dout.
The following figure shows how the sbiterr and dbiterr outputs
are generated in the Embedded FIFO Generator core. The output
signals are created by combining all the sbiterr and
dbiterr signals from the UltraRAM or block RAM
primitives using an OR gate. Because the RAM primitives can be cascaded in depth, when
sbiterr or dbiterr
is asserted, the error could have occurred in any of the RAM macros. For this reason,
these flags are not correlated to the data currently being read from the Embedded FIFO Generator core or to a read operation. For this
reason, when the dbiterr is flagged, assume that the
data in the entire FIFO has been corrupted and the user logic needs to take the
appropriate action. As an example, when dbiterr is
flagged, an appropriate action for the user logic is to halt all FIFO operation, reset
the FIFO, and restart the data transfer.
The sbiterr and dbiterr outputs are not registered and are generated combinatorially.