Write Data Count and Read Data Count - 1.0 English - PG327

When independent clock domains or common clock non-symmetric is selected, write data count (wr_data_count) and read data count (rd_data_count) signals are provided as an indication of the number of words in the FIFO relative to the write or read clock domains, respectively.

Consider the following when using the wr_data_count or rd_data_count ports.

• The wr_data_count and rd_data_count outputs are not an instantaneous representation of the number of words in the FIFO, but can instantaneously provide an approximation of the number of words in the FIFO.
• The wr_data_count and rd_data_count ports might skip values from clock cycle to clock cycle.
• Using non-symmetric aspect ratios, or running clocks which vary dramatically in frequency, will increase the disparity between the data count outputs and the actual number of words in the FIFO.