Native FIFO Configuration and Implementation - 1.0 English - PG327

Embedded FIFO Generator LogiCORE IP Product Guide (PG327)

Document ID
PG327
Release Date
2023-05-16
Version
1.0 English
The following table defines the supported memory and clock configurations.
Table 1. FIFO Configurations
Clock Domain Memory Type Non-symmetric Aspect Ratios First-word Fall-Through ECC Support Configurable Read Latency Support
Common Block RAM
Common Distributed RAM    
Common UltraRAM
Independent Block RAM
Independent Distributed RAM    

Common Clock: Block RAM, Distributed RAM, UltraRAM

This implementation category allows you to select block RAM, Distributed RAM, or UltraRAM and supports a common clock for write and read data accesses. The feature set supported for this configuration includes non-symmetric aspect ratios (different write and read port widths) for block/UltraRAM FIFOs, status flags (full, almost full, empty, and almost empty), and programmable empty and full flags generated with user-defined thresholds.

In addition, optional handshaking and error flags are supported (write acknowledge, overflow, read valid, and underflow), and an optional data count provides the number of words in the FIFO. The block/UltraRAM FIFO configuration also supports ECC.

Independent Clocks: block RAM and Distributed RAM

This implementation option allows you to select block RAM or Distributed RAM and supports independent clock domains for write and read data accesses. Operations in the read domain are synchronous to the read clock and operations in the write domain are synchronous to the write clock.

The feature set supported for this type of FIFO includes non-symmetric aspect ratios (different write and read port widths) for block RAM, status flags (full, almost full, empty, and almost empty), as well as programmable full and empty flags generated with user-defined thresholds. Optional read data count and write data count indicators provide the number of words in the FIFO relative to their respective clock domains. In addition, optional handshaking and error flags are available (write acknowledge, overflow, read valid, and underflow). The block RAM FIFO configuration also supports ECC.