The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
| Vivado IDE Parameter/Value | User Parameter/Value | Default Value |
|---|---|---|
| Basic Options | ||
| Interface Type | INTERFACE_TYPE | Native |
| FIFO Memory Type | FIFO_MEMORY_TYPE | AUTO |
| Cascade Height | CASCADE_HEIGHT | 0 |
| Clocking Options | CLOCK_DOMAIN | Common_Clock |
| Synchronization Stages | CDC_SYNC_STAGES | 2 |
| Related Clocks | RELATED_CLOCKS | 0 |
| Read Mode | READ_MODE | Standard |
| FIFO Read Latency | FIFO_READ_LATENCY | 1 |
| ECC Options | ||
| ECC Options | ECC_MODE | NO_ECC |
| Wr Chnl ECC Options | ECC_MODE_WDCH | NO_ECC |
| Rd Chnl ECC Options | ECC_MODE_RDCH | NO_ECC |
| Data Port Parameters | ||
| Write Depth | FIFO_WRITE_DEPTH | 2048 |
| Write Data Width | WRITE_DATA_WIDTH | 32 |
| Read Data Width | READ_DATA_WIDTH | 32 |
| Reset Options | ||
| Dout Reset Value | DOUT_RESET_VALUE | 0 |
| Full Flags Reset Value | FULL_RESET_VALUE | 0 |
| AXI4 Stream Config | ||
| FIFO Depth | FIFO_DEPTH_AXIS | 2048 |
| TDATA WIDTH | TDATA_WIDTH | 32 |
| TID WIDTH | TID_WIDTH | 8 |
| TDEST WIDTH | TDEST_WIDTH | 4 |
| TUSER WIDTH | TUSER_WIDTH | 4 |
| FIFO Application Type | ||
| FIFO Application Type | PACKET_FIFO | FALSE |
| Advanced Options | ||
| Handshake Flags | ||
| Enable Overflow | ENABLE_OVERFLOW | TRUE |
| Enable Underflow | ENABLE_UNDERFLOW | TRUE |
| Enable Almost Full | ENABLE_ALMOST_FULL | TRUE |
| Enable Almost Empty | ENABLE_ALMOST_EMPTY | TRUE |
| Enable Write Ack | ENABLE_WRITE_ACK | TRUE |
| Enable Read Data Valid | ENABLE_READ_DATA_VALID | TRUE |
| Data Count | ||
| Enable Write Data Count | ENABLE_WRITE_DATA_COUNT | TRUE |
| Enable Read Data Count | ENABLE_READ_DATA_COUNT | TRUE |
| Write Data Count Width | WR_DATA_COUNT_WIDTH | 12 |
| Read Data Count Width | RD_DATA_COUNT_WIDTH | 12 |
| Programmable Flags | ||
| Enable Programmable Full | ENABLE_PROGRAMMABLE_FULL | TRUE |
| Enable Programmable Empty | ENABLE_PROGRAMMABLE_EMPTY | TRUE |
| Programmable Full Threshold Assert Value | PROG_FULL_THRESH | 2043 |
| Programmable Empty Threshold Assert Value | PROG_EMPTY_THRESH | 5 |
| Power Savings Option | ||
| Wakeup Time | WAKEUP_TIME | Disable_Sleep |
| Enable Assertions | SIM_ASSERT_CHECK | FALSE |
| AXI4 Port Configuration | ||
| Common Width Configuration Options | ||
| ID Width | AXI_ID_WIDTH | 1 |
| Address Width | AXI_ADDR_WIDTH | 32 |
| Data Width | AXI_DATA_WIDTH | 32 |
| Write Channels | ||
| AWUSER Width | AXI_AWUSER_WIDTH | 1 |
| WUSER Width | AXI_WUSER_WIDTH | 1 |
| BUSER Width | AXI_BUSER_WIDTH | 1 |
| Read Channels | ||
| ARUSER Width | AXI_ARUSER_WIDTH | 1 |
| RUSER Width | AXI_RUSER_WIDTH | 1 |
| AXI4 Configuration | ||
| AW Channel FIFO Options | ||
| FIFO MEMORY TYPE | FIFO_MEMORY_TYPE_WACH | AUTO |
| FIFO DEPTH | FIFO_DEPTH_WACH | 2048 |
| W Channel FIFO Options | ||
| FIFO MEMORY TYPE | FIFO_MEMORY_TYPE_WDCH | AUTO |
| FIFO DEPTH | FIFO_DEPTH_WDCH | 2048 |
| B Channel FIFO Options | ||
| FIFO MEMORY TYPE | FIFO_MEMORY_TYPE_WRCH | AUTO |
| FIFO DEPTH | FIFO_DEPTH_WRCH | 2048 |
| AR Channel FIFO Options | ||
| FIFO MEMORY TYPE | FIFO_MEMORY_TYPE_RACH | AUTO |
| FIFO DEPTH | FIFO_DEPTH_RACH | 2048 |
| R Channel FIFO Options | ||
| FIFO MEMORY TYPE | FIFO_MEMORY_TYPE_RDCH | AUTO |
| FIFO DEPTH | FIFO_DEPTH_RDCH | 2048 |
| Write Channel | ||
| Handshake Flags | ||
| Enable Almost full | ENABLE_ALMOST_FULL_WDCH | TRUE |
| Enable Almost empty | ENABLE_ALMOST_EMPTY_WDCH | TRUE |
| Data Count | ||
| Enable Write Data Count | ENABLE_WRITE_DATA_COUNT_WDCH | TRUE |
| Write Data Count Width | WR_DATA_COUNT_WIDTH_WDCH | 12 |
| Enable read data count | ENABLE_READ_DATA_COUNT_WDCH | TRUE |
| Read data Count Width | RD_DATA_COUNT_WIDTH_WDCH | 12 |
| Programmable Flags | ||
| Enable programmable full | ENABLE_PROGRAMMABLE_FULL_WDCH | TRUE |
| Programmable Full Threshold Assert Value | PROG_FULL_THRESH_WDCH | 2043 |
| Enable Programming Empty | ENABLE_PROGRAMMABLE_EMPTY_WDCH | TRUE |
| Programmable Empty Threshold Assert Value | PROG_EMPTY_THRESH_WDCH | 5 |
| Read Channel | ||
| Handshake Flags | ||
| Enable almost full | ENABLE_ALMOST_FULL_RDCH | TRUE |
| Enable almost empty | ENABLE_ALMOST_EMPTY_RDCH | TRUE |
| Data Count | ||
| Enable Write Data Count | ENABLE_WRITE_DATA_COUNT_RDCH | TRUE |
| Wr data count width | WR_DATA_COUNT_WIDTH_RDCH | 12 |
| Enable read data count | ENABLE_READ_DATA_COUNT_RDCH | TRUE |
| Rd data count width | RD_DATA_COUNT_WIDTH_RDCH | 12 |
| Programmable Flags | ||
| Enable programmable full | ENABLE_PROGRAMMABLE_FULL_RDCH | TRUE |
| Prog full thresh | PROG_FULL_THRESH_RDCH | 2043 |
| Enable programmable empty | ENABLE_PROGRAMMABLE_EMPTY_RDCH | TRUE |
| Prog empty thresh | PROG_EMPTY_THRESH_RDCH | 5 |