To understand the nature of FIFO designs, it is important to understand how pipelining is used to maximize performance and implement synchronization logic for clock-domain crossing. Data written into the write interface might take multiple clock cycles before it can be accessed on the read interface.
Synchronization Considerations
FIFOs with independent write and read clocks require that interface signals be used only in their respective clock domains. The independent clocks FIFO handles all synchronization requirements, enabling you to cross between two clock domains that have no relationship in frequency or phase.
The following figure shows the signals with respect to their clock domains. All signals are synchronous to a specific clock.
For write operations, the write enable signal (wr_en
) and
data input (din
) are synchronous to wr_clk
. For
read operations, the read enable (rd_en
) and data output
(dout
) are synchronous to rd_clk
. All status
outputs are synchronous to their respective clock domains and can only be used in
that clock domain. The performance of the FIFO can be measured by independently
constraining the clock period for the wr_clk
and
rd_clk
input signals.
The interface signals are evaluated on their rising clock edge
(wr_clk
and rd_clk
). They can be made
falling-edge active (relative to the clock source) by inserting an inverter between
the clock source and the FIFO clock inputs. This inverter is absorbed into the
internal FIFO control logic and does not cause a decrease in performance or increase
in logic utilization.