Top-Level Registers - 5.2 English

0x0000

Control

R/W

Bit[0] = ap_start (R/W/COH) ⁽¹⁾

Bit[1] = ap_done (R/COR) ⁽¹⁾

Bit[2] = ap_idle (R)

Bit[3] = ap_ready (R)

Bit[5] = Flush pending AXI transactions (R/W) ⁽²⁾

Bit[6] = Flush done (R)

Bit[7] = auto_restart (R/W)

Others = reserved

0x0004

Global Interrupt Enable

R/W

Bit[0] = Global interrupt enable

Others = Reserved

0x0008

IP Interrupt Enable

Bit[0] = ap_done

Bit[1] = ap_ready

Others = reserved

0x000C

IP Interrupt Status Register

R/TOW ⁽¹⁾

Bit[0] = ap_done

Bit[1] = ap_ready

Others = Reserved

0x0010

Width

R/W

Active width of background.

0x0018

Height

R/W

Active height of background.

0x0028

Background R or Y

R/W

Red or Y value of background color

0x0030

Background U or G

R/W

Green or U value of background color

0x0038

Background V or B

R/W

Blue or V value of background color

0x0040

Layer enable

R/W

Bit[0] = Master layer is enabled/disabled

Bit[1] = Overlay Layer 1 is enabled/disabled

…

Bit[16] = Overlay Layer 16 is enabled/disabled

Bit[23] = Logo layer is enabled/disabled

Notes:

1. TOW = Toggle on Write, COH = Clear on Handshake, COR = Clear on Read

2. BIT[5] and BIT[6] are applicable only for memory based layers

3. Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in section S_AXILITE Control Register Map of Vitis High-Level Synthesis User Guide (UG1399) [Ref 13] . These registers’ definitions may have some additional bits; however, in the current IP, we are accessing only bits mentioned in Table: Top-Level Registers . Therefore, only these bits need to be considered while accessing the above registers.