This chapter provides two example systems that include the Video Mixer . One is a simulation example design and the other one is a synthesizable example design. Important system-level aspects when designing with the Video Mixer are highlighted in these example designs, including:
• Video Mixer usage with memory mapped AXI4 interface memory layers.
• Typical usage of the Video Mixer with other cores.
• Video Mixer usage with AXI4-Stream interface layers (streaming input comes from the Video Frame Buffer Read IP)
• Run-time configuration of the Video Mixer by programming registers on-the-fly.
The supported platforms are listed in Table: Supported Platforms .
Development Boards |
Additional Hardware |
Processor |
---|---|---|
KC705 |
N/A |
MicroBlaze™ |
ZCU102 |
N/A |
psu_cortexa53_0 |
ZCU104 |
N/A |
psu_cortexa53_0 |
ZCU106 |
N/A |
psu_cortexa53_0 |
VCK190 |
N/A |
CIPS |
To open the example project, perform the following:
1. Select the Video Mixer IP from the AMD Vivado ™ IP catalog.
2. Double-click the selected IP or right-click the IP and select Customize IP from the menu.
3. Configure the build-time parameters in the Customize IP window and click OK . The Vivado IDE generates an example design matching the build-time configuration.
4. In the Generate Output Products window, select Generate or Skip . If Generate is selected, the IP output products are generated after a brief moment.
5. Right-click Video Mixer in Sources panel and select Open IP Example Design from the menu.
6. In the Open IP Example Design window, select example project directory and click OK . The Vivado software then runs automation to generate the example design in the selected directory.
The generated project contains two example designs. This Figure shows the Source panel of the example project. Synthesizable example block design, along with top-level file, resides in Design Sources catalog. A corresponding constraint file is also provided for the synthesizable example design. Simulation example design files (including block design file, SystemVerilog test bench and another task file) are under Simulation Sources .