Revision History - 5.2 English

Video Mixer LogiCORE IP Product Guide (PG243)

Document ID
PG243
Release Date
2024-01-02
Version
5.2 English

The following table shows the revision history for this document.

Date

Version

Revision

01/02/2024

5.2

Updated IP Facts .

Editorial updates.

10/19/2022

5.2

Updated Layer Width (0x0#18) Register

Added note for Line Buffer Width in Design Flow Steps

04/27/2022

5.2

Updated Table: Top-Level Registers .

Updated Table: CSC Coefficient Registers .

Updated the Control (0x0000) Register section.

10/27/2021

5.2

Updated to support eight samples per clock.

08/06/2021

5.2

Updated Table: Supported Platforms .

Updated the Upgrading section.

02/04/2021

5.1

Updated Example Design with Vitis application flow for v5.1.

06/10/2020

5.0

Added CSC Coefficient Registers table.

Added Enable CSC Coefficient Registers parameter in the GUI.

Updated Figure 4-1.

Updated Table 4-1.

Updated Upgrading in the Vivado Design Suite section.

12/06/2019

4.0

Updated for Example Design with Vitis application flow.

Added Layer 0 registers.

05/22/2019

4.0

Updated to support up to 16 overlay layers.

12/05/2018

3.0

Updated to show one main layer and eight overlay layers support.

04/04/2018

3.0

Updated to support 8 overlay layers.

Added support for BGR8.

10/04/2017

2.0

Added second buffer pointer for semi-planar formats.

Added 64-bit address support for memory mapped AXI4 interface.

Register map offsets re-ordered to handle both 32 and 64-bit addressing.

Added UYVY8 and BGRX8 memory formats.

Added per pixel alpha streaming formats RGBA and YUVA444 .

04/05/2017

1.0

Added BGRA8, Y_UV10, Y_UV10_420, Y8, and Y10 to Memory Mapped AXI4 Interface.

10/05/2016

1.0

Added YUV 4:2:0.

Updated Features in IP Facts.

Updated SDK directory link in IP Facts table.

Updated Feature Summary section.

Added RGBA8 to Y_UV8_420 sections.

Updated description for Layer Buffer (0x0048+i*8) Register section.

Added 0x4 0000 Logo Alpha Buffer table.

Updated description in Logo Red Buffer (0x1 0000) Register.

Updated description in General Design Guidelines section.

Updated Alpha Blending section.

Updated description to Layer Settings and Logo Layer Settings in Design Flow Steps chapter.

Added Enable Logo per Pixel Alpha in Vivado IDE Parameter to User Parameter Relationship table.

Updated Prerequisites section.

04/06/2016

1.0

Initial Xilinx release.