Layer Stride (0x0#20) Register - 5.2 English

Video Mixer LogiCORE IP Product Guide (PG243)

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5.2 English

This register is not applicable if the layer is a streaming layer. If it is a memory layer, the layer stride determines the number of bytes from one row of pixels in memory to the next row of pixels in memory. When a video frame is stored in memory, the memory buffer might contain extra padding bytes after each row of pixels. The padding bytes only affect how the image is stored in memory, but does not affect how the image is displayed.

Padding bytes are necessary to make sure that every row of pixels starts at an address that is aligned with the size of the data on the memory mapped AXI4 interface. Therefore, layer stride needs to be a multiple of the memory mapped AXI4 data size. For the Video Mixer , the data size of the memory mapped AXI4 interface is 64 × Samples per Clock bits, that is, 64, 128, 256, and 512 bits for 1, 2, 4, and 8 samples per clock, respectively.